Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, where the first level is overlaid by a first isolation layer; a second level including single crystal second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, and where the first isolation layer and the second isolation layer are separated by a distance of less than four microns.

Abstract: A 3D semiconductor wafer, the wafer including: a first device, where the first device includes a first level, the first level including first transistors, and where the first device includes a second level, the second level including first interconnections; a second device overlaying the first device, where the second device includes a third level, the third level including second transistors, and where the second device includes a fourth level, the fourth level including second interconnections, where the first device is substantially larger in area than the second device; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes a Phase Lock Loop (“PLL”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.

Abstract: An electrical passenger car, the electrical passenger car including: an electrically driven motor; differential speed control; and wheels, where the wheels include a first front wheel, a second front wheel, a first back wheel, and a second back wheel, where at least one of the wheels has a radius larger than 80 cm, where the differential speed control includes an ability to have a turning speed of the first front wheel greater than a turning speed of the second front wheel, and where the electrical passenger car is designed to travel for a greater distance for the same axial to wheel friction energy loss than a similar electrical passenger car having wheels of a smaller radius.

Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors, contacts, and a first metal layer, where a portion of the first single crystal transistors are interconnected, where the interconnected includes the first metal layer and the contacts, and where the portion of the first single crystal transistors are interconnected forms memory control circuits; a second level overlaying the first level, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; a fourth level overlaying the third level, the fourth level including a plurality of fourth transistors; and a second metal layer overlaying the fourth level, where the plurality of second transistors are aligned to the plurality of first transistors with a less than 40 nm alignment error.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the plurality of logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes an Serializer/Deserializer (“SerDes”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.

Abstract: A method to form a 3D semiconductor device, the method including: providing a first wafer including first circuits including transistors and interconnection; preparing a second wafer including a silicon layer; performing growth of an epitaxial layer on top of the silicon layer, the epitaxial layer including non-silicon atoms, forming second circuits over the second wafer, the second circuits including transistors and interconnection; transferring and then bonding the second wafer on top of the first wafer; and then thinning the second wafer to a thickness of less than ten microns.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer; at least one first metal layer above the first single crystal layer; a second metal layer above the first metal layer; a plurality of first transistors atop the second metal layer; a plurality of second transistors atop the second transistors; a plurality of third transistors atop the second transistors; a third metal layer above the plurality of third transistors: a fourth metal layer above the third metal layer; and a second single crystal layer above the fourth metal layer; and a plurality of connecting metal paths from the fourth metal layer to the second metal layer, where at least one of the plurality of third transistors is aligned to at least one of the plurality of first transistors with less than 40 nm alignment error, where the fourth metal layer is providing global power distribution to the device.

Abstract: A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor, the memory peripherals transistor is overlaying the second transistor or is underneath the first transistor, where the second memory cell overlays the first memory cell at a distance of less than 200 nm, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.

Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, where the first level is overlaid by a first isolation layer; a second level including single crystal second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, and where the first isolation layer and the second isolation layer are separated by a distance of less than four microns.

Abstract: A 3D semiconductor memory, the memory including: a first level including first memory cells, first transistors, and a first control line, where the first memory cells each include one of the first transistors; a second level including second memory cells, second transistors, and a second control line, where the second memory cells each include one of the second transistors, where the second level overlays the first level, where the second control line and the first control line have been processed following the same lithography step and accordingly are self-aligned, where the first control line is directly connected to each source or drain of at least five of the first transistors, and where the second control line is directly connected to each source or drain of at least five of the second transistors; and an oxide layer disposed between the first control line and the second control line.

Abstract: An electrical passenger car, the electrical passenger car including: an electrically driven motor; and wheels, where the wheels include a first wheel, a second wheel, a third wheel, and a fourth wheel, where the first wheel and the second wheel have a radius 20 percent larger than the third wheel and the fourth wheel, where the electrical passenger car includes a total weight, where the electrical passenger car includes a center of gravity designed so that greater than 50% of the total weight will be over the first wheel and the second wheel, where the electrical passenger car is designed to travel for a greater distance for the same axial to wheel friction energy loss than a similar electrical passenger car having wheels of a smaller radius, and where the second wheel width is equal to or less than the third wheel width.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer; at least one first metal layer above the first single crystal layer; a second metal layer above the first metal layer; a plurality of first transistors atop the second metal layer; a plurality of second transistors atop the second transistors; a plurality of third transistors atop the second transistors; a third metal layer above the plurality of third transistors: a fourth metal layer above the third metal layer; and a second single crystal layer above the fourth metal layer; and a plurality of connecting metal paths from the fourth metal layer to the second metal layer, where at least one of the plurality of third transistors is aligned to at least one of the plurality of first transistors with less than 40 nm alignment error, where the fourth metal layer is providing global power distribution to the device.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors overlaying the at least one first metal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell overlaying the memory peripheral circuits; and a second memory cell overlaying the first memory cell, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type.

Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and is controlled by a third control line, where the second transistor is overlaying the first transistor and is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and third control line, and where the first transistor, the second transistor and the third transistor are all aligned to each other with less than 100 nm misalignment.

Abstract: A 3D device, the device including: a first stratum of first bit-cell memory arrays; a second stratum of second bit-cell memory arrays; and a third stratum, where the second stratum overlays the first stratum, where the third stratum overlays the second stratum, where the third stratum includes a plurality of word-line decoders to control the first bit-cell memory arrays and the second bit-cell memory arrays.

Abstract: A 3D semiconductor device, the device comprising: a first single crystal layer comprising a plurality of first transistors; at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates; a plurality of second transistors overlaying said first single crystal layer; a plurality of third transistors overlaying said plurality of second transistors; a top metal layer overlying said third transistors; first circuits underlying said first single crystal layer; second circuits overlying said top metal layer; a first set of connections underlying said at least one metal layer, wherein said first set of connections connects said first transistors to said first circuits; a second set of connections overlying said top metal layer, wherein said second set of connections connects said first transistors to said second circuits, and wherein said first set of connections comprises a through silicon via (TSV).

Abstract: A semiconductor device including: a first layer including a first memory cell, the first memory cell including a first transistor; a second layer including a second memory cell, the second memory cell including a second transistor; a periphery layer including a memory peripherals transistor, the periphery layer is disposed underneath the first layer; a memory including at least the first memory cell and the second memory cell, where the second memory cell overlays the first memory cell, where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where a peripherals circuit includes the memory peripherals transistor and controls the memory; a first external connections underlying the periphery layer, the first external connections includes connections from the device to a first external device; and a second external connections overlying the second layer, the second external connections includes connections from the dev

Abstract: A semiconductor device including: a first memory cell including a first transistor; and a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor is self-aligned to the first transistor, where access to the first memory cell is controlled by at least one junction-less transistor, and where the junction-less transistor is not part of the first memory cell and the second memory cell.

Abstract: A 3D semiconductor wafer, the wafer including: a first device, where the first device includes a first level, the first level including first transistors, and where the first device includes a second level, the second level including first interconnections; a second device overlaying the first device, where the second device includes a third level, the third level including second transistors, and where the second device includes a fourth level, the fourth level including second interconnections, where the first device is substantially larger in area than the second device; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors.