3D memory device and structure
A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and is controlled by a third control line, where the second transistor is overlaying the first transistor and is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and third control line, and where the first transistor, the second transistor and the third transistor are all aligned to each other with less than 100 nm misalignment.
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This application is a continuation in part of U.S. patent application Ser. No. 14/199,755 filed on Mar. 6, 2014, which is a continuation of U.S. patent application Ser. No. 13/685,751 filed on Nov. 27, 2012, now U.S. Pat. No. 8,742,476 issued on Jun. 3, 2014, the entire contents all the above references are incorporated herein by reference.
This application is a continuation in part of U.S. patent application Ser. No. 15/201,430 filed on Jul. 2, 2016, which is a continuation in part of U.S. patent application Ser. No. 14/626,563 filed on Feb. 19, 2015, now U.S. Pat. No. 9,385,088 issued on Jul. 5, 2016, which is a continuation of U.S. patent application Ser. No. 14/017,266 filed on Sep. 3, 2013, which is a continuation of U.S. patent application Ser. No. 13/099,010 filed on May 2, 2011, now U.S. Pat. No. 8,581,349 issued on Nov. 12, 2013, which is a continuation-in-part of U.S. patent application Ser. No. 12/951,913 filed on Nov. 22, 2010, now U.S. Pat. No. 8,536,023 issued on Sep. 17, 2013, which is a continuation-in part of U.S. patent application Ser. No. 12/904,119 filed on Oct. 13, 2010, now U.S. Pat. No. 8,476,145 issued on Jul. 2, 2013, the entire contents all the above references are incorporated herein by reference.
In addition, U.S. patent application Ser. No. 15/201,430 filed on Jul. 2, 2016, is a continuation-in part of U.S. patent application Ser. No. 13/016,313 filed on Jan. 28, 2011, now U.S. Pat. No. 8,362,482 issued on Jan. 29, 2013, which is a continuation-in part of U.S. patent application Ser. No. 12/970,602 filed on Dec. 16, 2010, which is a continuation-in part of U.S. patent application Ser. No. 12/949,617 filed on Nov. 18, 2010, now U.S. Pat. No. 8,754,533 issued on Jun. 17, 2014, which is a continuation-in part of U.S. patent application Ser. No. 12/900,379 filed on Oct. 7, 2010, now U.S. Pat. No. 8,395,191 issued on Mar. 12, 2013, which is a continuation-in part of U.S. patent application Ser. No. 12/847,911 filed on Jul. 30, 2010, now U.S. Pat. No. 7,960,242 issued on Jun. 14, 2011, which is a continuation-in part of U.S. patent application Ser. No. 12/792,673 filed on Jun. 2, 2010, now U.S. Pat. No. 7,964,916 issued on Jun. 21, 2011, which is a continuation-in part of U.S. patent application Ser. No. 12/706,520 filed on Feb. 16, 2010, which is a continuation-in part of U.S. patent application Ser. No. 12/577,532 filed on Oct. 12, 2009, the entire contents of all the above references are incorporated herein by reference.BACKGROUND OF THE INVENTION
1. Field of the Invention
This application relates to the general field of Integrated Circuit (IC) devices and fabrication methods, and more particularly to multilayer or Three Dimensional Integrated Circuit (3D-IC) devices and fabrication methods.
2. Discussion of Background Art
Over the past 40 years, there has been a dramatic increase in functionality and performance of Integrated Circuits (ICs). This has largely been due to the phenomenon of “scaling”; i.e., component sizes within ICs have been reduced (“scaled”) with every successive generation of technology. There are two main classes of components in Complementary Metal Oxide Semiconductor (CMOS) ICs, namely transistors and wires. With “scaling”, transistor performance and density typically improve and this has contributed to the previously-mentioned increases in IC performance and functionality. However, wires (interconnects) that connect together transistors degrade in performance with “scaling”. The situation today is that wires dominate the performance, functionality and power consumption of ICs.
3D stacking of semiconductor devices or chips is one avenue to tackle the wire issues. By arranging transistors in 3 dimensions instead of 2 dimensions (as was the case in the 1990s), the transistors in ICs can be placed closer to each other. This reduces wire lengths and keeps wiring delay low.
There are many techniques to construct 3D stacked integrated circuits or chips including:
- Through-silicon via (TSV) technology: Multiple layers of transistors (with or without wiring levels) can be constructed separately. Following this, they can be bonded to each other and connected to each other with through-silicon vias (TSVs).
- Monolithic 3D technology: With this approach, multiple layers of transistors and wires can be monolithically constructed. Some monolithic 3D and 3DIC approaches are described in U.S. Pat. Nos. 8,273,610, 8,557,632, 8,298,875, 8,642,416, 8,362,482, 8,378,715, 8,379,458, 8,450,804, 8,476,145, 8,536,023, 8,574,929, 8,581,349, 8,642,416, 8,687,399, 8,742,476, 8,674,470, 8,803,206, 8,836,073, 8,902,663, 8,994,404, 9,021,414, 9,023,688, 9,030,858, 9,117,749, 9,142,553, 9,219,005, 9,385,088, 9,406,670, 9,460,978, 9,509,313; U.S. patent publications 2011/0092030, 2016/0218046; and pending U.S. Patent Applications 62/077,280, 62/042,229, 61/932,617, Ser. Nos. 14/607,077, 14/642,724, 62/139,636, 62/149,651, 62/198,126, 62/239,931, 62/246,054, 62/307,568, 62/297,857, Ser. Nos. 15/095,187, 15/150,395, 15/173,686, 62/383,463, 62/440,720, 62/443,751, Ser. No. 15/243,941, PCT/US16/52726, 62/406,376, 62/432,575, 62/440,720, 62/297,857, Ser. Nos. 15/333,138, 15/344,562, and 15/351,389. The entire contents of the foregoing patents, publications, and applications are incorporated herein by reference.
- Electro-Optics: There is also work done for integrated monolithic 3D including layers of different crystals, such as U.S. Pat. Nos. 8,283,215, 8,163,581, 8,753,913, 8,823,122, 9,197,804, 9,419,031; and U.S. patent publication 2016/0064439. The entire contents of the foregoing patents, publications, and applications are incorporated herein by reference.
Regardless of the technique used to construct 3D stacked integrated circuits or chips, heat removal is a serious issue for this technology. For example, when a layer of circuits with power density P is stacked atop another layer with power density P, the net power density is 2P. Removing the heat produced due to this power density is a significant challenge. In addition, many heat producing regions in 3D stacked integrated circuits or chips have a high thermal resistance to the heat sink, and this makes heat removal even more difficult.
Several solutions have been proposed to tackle this issue of heat removal in 3D stacked integrated circuits and chips. These are described in the following paragraphs.
Publications have suggested passing liquid coolant through multiple device layers of a 3D-IC to remove heat. This is described in “Microchannel Cooled 3D Integrated Systems”, Proc. Intl. Interconnect Technology Conference, 2008 by D. C. Sekar, et al., and “Forced Convective Interlayer Cooling in Vertically Integrated Packages,” Proc. Intersoc. Conference on Thermal Management (ITHERM), 2008 by T. Brunschweiler, et al.
Thermal vias have been suggested as techniques to transfer heat from stacked device layers to the heat sink. Use of power and ground vias for thermal conduction in 3D-ICs has also been suggested. These techniques are described in “Allocating Power Ground Vias in 3D ICs for Simultaneous Power and Thermal Integrity” ACM Transactions on Design Automation of Electronic Systems (TODAES), May 2009 by Hao Yu, Joanna Ho and Lei He.
Other techniques to remove heat from 3D Integrated Circuits and Chips will be beneficial.
Additionally the 3D technology according to some embodiments of the invention may enable some very innovative IC alternatives with reduced development costs, increased yield, and other illustrative benefits.SUMMARY
The invention may be directed to multilayer or Three Dimensional Integrated Circuit (3D IC) devices and fabrication methods.
In one aspect, a 3D integrated circuit device, comprising: a first transistor; a second transistor; and a third transistor, wherein said third transistor is overlaying said second transistor and is controlled by a third control line, wherein said second transistor is overlaying said first transistor and is controlled by a second control line, wherein said first transistor is part of a control circuit controlling said second control line and third control line, and wherein said first transistor, said second transistor and said third transistor are all aligned to each other with less than 100 nm misalignment.
In another aspect, a 3D integrated circuit device, comprising: a first transistor; a second transistor; and a third transistor, wherein said third transistor is overlaying said second transistor and is controlled by a third control line, wherein said second transistor is overlaying said first transistor and is controlled by a second control line, wherein said second transistor comprises a schottky barrier, and wherein said first transistor, said second transistor and said third transistor are all aligned to each other with less than 100 nm misalignment.
In another aspect, A 3D integrated circuit device, comprising: a first transistor; a first memory cell comprising a second transistor; and a second memory cell comprising a third transistor, wherein said third transistor is overlaying said second transistor and said second transistor is overlaying said first transistor, wherein said first transistor is part of a control circuit controlling said first and second memory cell, wherein said first transistor, said second transistor and said third transistor are all aligned to each other with less than 100 nm misalignment, and wherein said second transistor is connected to said third transistor with an ohmic connection.
Various embodiments of the invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which:
An embodiment of the invention is now described with reference to the drawing figures. Persons of ordinary skill in the art will appreciate that the description and figures illustrate rather than limit the invention and that in general the figures are not drawn to scale for clarity of presentation. Such skilled persons will also realize that many more embodiments are possible by applying the inventive principles contained herein and that such embodiments fall within the scope of the invention which is not to be limited except by the appended claims.
Some drawing figures may describe process flows for building devices. The process flows, which may be a sequence of steps for building a device, may have many structures, numerals and labels that may be common between two or more adjacent steps. In such cases, some labels, numerals and structures used for a certain step's figure may have been described in the previous steps' figures.
Step (A): A silicon dioxide layer 104 is deposited above the generic bottom layer 102.
Step (B): The top layer of doped or undoped silicon 106 to be transferred atop the bottom layer is processed and an oxide layer 108 is deposited or grown above it.
Step (C): Hydrogen is implanted into the top layer silicon 106 with the peak at a certain depth to create the hydrogen plane 110. Alternatively, another atomic species such as helium or boron can be implanted or co-implanted.
Step (D): The top layer wafer shown after Step (C) is flipped and bonded atop the bottom layer wafer using oxide-to-oxide bonding.
Step (E): A cleave operation is performed at the hydrogen plane 110 using an anneal. Alternatively, a sideways mechanical force may be used. Further details of this cleave process are described in “Frontiers of silicon-on-insulator,” J. Appl. Phys. 93, 4955-4978 (2003) by G. K. Celler and S. Cristoloveanu (“Celler”) and “Mechanically induced Si layer transfer in hydrogen-implanted Si wafers,” Appl. Phys. Lett., vol. 76, pp. 1370-1372, 1000 by K. Henttinen, I. Suni, and S. S. Lau (“Hentinnen”). Following this, a Chemical-Mechanical-Polish (CMP) is done.
Step (A): Peripheral circuits with tungsten wiring 202 are first constructed and above this oxide layer 204 is deposited.
A floating-body DRAM has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels (2) some of the memory cell control lines, e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
While many of today's memory technologies rely on charge storage, several companies are developing non-volatile memory technologies based on resistance of a material changing. Examples of these resistance-based memories include phase change memory, Metal Oxide memory, resistive RAM (RRAM), memristors, solid-electrolyte memory, ferroelectric RAM, conductive bridge RAM, and MRAM. Background information on these resistive-memory types is given in “Overview of candidate device technologies for storage-class memory,” IBM Journal of Research and Development, vol. 52, no. 4.5, pp. 449-464, July 2008 by Burr, G. W.; Kurdi, B. N.; Scott, J. C.; Lam, C. H.; Gopalakrishnan, K.; Shenoy, R. S.
Step (A): Peripheral circuits 302 are first constructed and above this oxide layer 304 is deposited.
A 3D resistance change memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines, e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates that are simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
Step (A): Peripheral circuits with tungsten wiring 402 are first constructed and above this oxide layer 404 is deposited.
A 3D resistance change memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines—e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.
While resistive memories described previously form a class of non-volatile memory, others classes of non-volatile memory exist. NAND flash memory forms one of the most common non-volatile memory types. It can be constructed of two main types of devices: floating-gate devices where charge is stored in a floating gate and charge-trap devices where charge is stored in a charge-trap layer such as Silicon Nitride. Background information on charge-trap memory can be found in “Integrated Interconnect Technologies for 3D Nanoelectronic Systems”, Artech House, 2009 by Bakir and Meindl (“Bakir”) and “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by Hang-Ting Lue, et al. The architectures shown in
Step (A): Peripheral circuits 502 are first constructed and above this oxide layer 504 is deposited.
Lithography and etch are utilized to define gate regions. Gates of the NAND string 536 as well gates of select gates of the NAND string 538 are defined.
A 3D charge-trap memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines—e.g., bit lines BL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut. This use of single-crystal silicon obtained with ion-cut is a key differentiator from past work on 3D charge-trap memories such as “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by Hang-Ting Lue, et al. that used polysilicon.
An alternate method to obtain low temperature 3D compatible CMOS transistors residing in the same device layer of silicon is illustrated in
Persons of ordinary skill in the art will appreciate that the low temperature 3D compatible CMOS transistor formation method and techniques described in
Persons of ordinary skill in the art will appreciate that when multiple layers of doped or undoped single crystal silicon and an insulator, such as, for example, silicon dioxide, are formed as described above (e.g. additional Si/SiO2 layers 3024 and 3026 and first Si/SiO2 layer 3022), that there are many other circuit elements which may be formed, such as, for example, capacitors and inductors, by subsequent processing. Moreover, it will also be appreciated by persons of ordinary skill in the art that the thickness and doping of the single crystal silicon layer wherein the circuit elements, such as, for example, transistors, are formed, may provide a fully depleted device structure, a partially depleted device structure, or a substantially bulk device structure substrate for each layer of a 3D IC or the single layer of a 2D IC.
Alternatively, another process could be used for forming activated source-drain regions. Dopant segregation techniques (DST) may be utilized to efficiently modulate the source and drain Schottky barrier height for both p and n type junctions. Metal or metals, such as platinum and nickel, may be deposited, and a silicide, such as Ni0.9Pt0.1Si, may formed by thermal treatment or an optical treatment, such as a laser anneal, following which dopants for source and drain regions may be implanted, such as arsenic and boron, and the dopant pile-up is initiated by a low temperature post-silicidation activation step, such as a thermal treatment or an optical treatment, such as a laser anneal. An alternate DST is as follows: Metal or metals, such as platinum and nickel, may be deposited, following which dopants for source and drain regions may be implanted, such as arsenic and boron, followed by dopant segregation induced by the silicidation thermal budget wherein a silicide, such as Ni0.9Pt0.1Si, may formed by thermal treatment or an optical treatment, such as a laser anneal. Alternatively, dopants for source and drain regions may be implanted, such as arsenic and boron, following which metal or metals, such as platinum and nickel, may be deposited, and a silicide, such as Ni0.9Pt0.1Si, may formed by thermal treatment or an optical treatment, such as a laser anneal. Further details of these processes for forming dopant segregated source-drain regions are described in “Low Temperature Implementation of Dopant-Segregated Band-edger Metallic S/D junctions in Thin-Body SOI p-MOSFETs”, Proceedings IEDM, 2007, pp 147-150, by G. Larrieu, et al.; “A Comparative Study of Two Different Schemes to Dopant Segregation at NiSi/Si and PtSi/Si Interfaces for Schottky Barrier Height Lowering”, IEEE Transactions on Electron Devices, vol. 55, no. 1, January 2008, pp. 396-403, by Z. Qiu, et al.; and “High-k/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length”, IEEE Electron Device Letters, vol. 31, no. 4, April 2010, pp. 275-277, by M. H. Khater, et al.
This embodiment of the invention advantageously uses this low-temperature source-drain formation technique and layer transfer techniques and produces 3D integrated circuits and chips.
Ion-cut may need anneals to remove defects at temperatures higher than 400° C., so techniques to remove defects without the acceptor wafer seeing temperatures higher than 400° C. may be desirable.
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Persons of ordinary skill in the art will appreciate that the illustrations in
A planar n-channel JFET or JLT with an optional integrated heat shield/spreader suitable for a monolithic 3D IC may be constructed as follows. Being bulk conduction devices rather than surface conduction devices, the JFET and JLT may provide an improved transistor variability control and conduction channel electrostatic control. Sub-threshold slope, DIBL, and other short channel effects are greatly improved due to the firm gate electrostatic control over the channel. Moreover, a heat spreading, heat conducting and/or optically reflecting material layer or layers may be incorporated between the sensitive metal interconnect layers and the layer or regions being optically irradiated and annealed to repair defects in the crystalline 3D-IC layers and regions and to activate semiconductor dopants in the crystalline layers or regions of a 3D-IC without harm to the sensitive metal interconnect and associated dielectrics. Furthermore, a buried doped layer and channel dopant shaping, even to an un-doped channel, may allow for efficient adaptive and dynamic body biasing to control the transistor threshold and threshold variations, the concepts shown in FIG. 32 of incorporated U.S. Pat. No. 8,581,349 may be applied to the JFET. As well, the back plane and body bias tap concepts shown in FIG. 46 of incorporated U.S. Pat. No. 8,581,349 may be utilized for the JFET and JLT devices. As one of ordinary skill in the art would understand, many other types of transistors, such as a FinFet transistor, could be made utilizing similar concepts in their construction.
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A thermal conduction path may be constructed from the devices in the upper layer, the transferred donor layer and formed transistors, to the acceptor wafer substrate and associated heat sink. The thermal conduction path from the JFET or JLT transistor device and other devices on the top (second) crystalline layer, for example, raised S/D regions 832, to the acceptor wafer heat sink 897 may include source & drain contacts 840, second device layer metal interconnect 861, TLV 860, shield path connect 885 (shown as twice), shield path via 883 (shown as twice), metal interconnect 881, first (acceptor) layer metal interconnect 891, acceptor wafer transistors and devices 893, and acceptor substrate 895. The elements of the thermal conduction path may include materials that have a thermal conductivity greater than 10 W/m-K, for example, copper (about 400 W/m-K), aluminum (about 237 W/m-K), and Tungsten (about 173 W/m-K), and may include material with thermal conductivity lower than 10 W/m-K but have a high heat transfer capacity due to the wide area available for heat transfer and thickness of the structure (Fourier's Law), such as, for example, acceptor substrate 895. The elements of the thermal conduction path may include materials that are thermally conductive but may not be substantially electrically conductive, for example, Plasma Enhanced Chemical Vapor Deposited Diamond Like Carbon-PECVD DLC (about 1000 W/m-K), and Chemical Vapor Deposited (CVD) graphene (about 5000 W/m-K). The acceptor wafer interconnects may be substantially surrounded by BEOL isolation 896. The heat removal apparatus, which may include acceptor wafer heat sink 897, may include an external surface from which heat transfer may take place by methods such as air cooling, liquid cooling, or attachment to another heat sink or heat spreader structure.
Formation of CMOS, such as for the described JFETs or JLTs, in one transferred layer and the orthogonal connect strip methodology may be found as illustrated in at least FIGS. 30-33, 73-80, and 94 and related specification sections of U.S. Pat. No. 8,273,610, and may be applied to at least the
Persons of ordinary skill in the art will appreciate that the illustrations in
While ion-cut has been described in previous sections as the method for layer transfer, several other procedures exist that fulfill the same objective. These include:
- Lift-off or laser lift-off: Background information for this technology is given in “Epitaxial lift-off and its applications”, 1993 Semicond. Sci. Technol. 8 1124 by P Demeester et al. (“Demeester”).
- Porous-Si approaches such as ELTRAN: Background information for this technology is given in “Eltran, Novel SOI Wafer Technology”, JSAP International, Number 4, July 2001 by T. Yonehara and K. Sakaguchi (“Yonehara”) and also in “Frontiers of silicon-on-insulator,” J. Appl. Phys. 93, 4955-4978, 2003 by G. K. Celler and S. Cristoloveanu (“Celler”).
- Time-controlled etch-back to thin an initial substrate, Polishing, Etch-stop layer controlled etch-back to thin an initial substrate: Background information on these technologies is given in Celler and in U.S. Pat. No. 6,806,171.
- Rubber-stamp based layer transfer: Background information on this technology is given in “Solar cells sliced and diced”, 19 May 2010, Nature News.
The above publications giving background information on various layer transfer procedures are incorporated herein by reference. It is obvious to one skilled in the art that one can form 3D integrated circuits and chips as described in this document with layer transfer schemes described in these publications.
Some embodiments of the invention may include alternative techniques to build IC (Integrated Circuit) devices including techniques and methods to construct 3D IC systems. Some embodiments of the invention may enable device solutions with far less power consumption than prior art. The device solutions could be very useful for the growing application of mobile electronic devices and mobile systems such as, for example, mobile phones, smart phone, and cameras, those mobile systems may also connect to the internet. For example, incorporating the 3D IC semiconductor devices according to some embodiments of the invention within the mobile electronic devices and mobile systems could provide superior mobile units that could operate much more efficiently and for a much longer time than with prior art technology.
Smart mobile systems may be greatly enhanced by complex electronics at a limited power budget. The 3D technology described in the multiple embodiments of the invention would allow the construction of low power high complexity mobile electronic systems. For example, it would be possible to integrate into a small form function a complex logic circuit with high density high speed memory utilizing some of the 3D DRAM embodiments of the invention and add some non-volatile 3D NAND charge trap or RRAM described in some embodiments of the invention. Mobile system applications of the 3DIC technology described herein may be found at least in FIG. 156 of U.S. Pat. No. 8,273,610, the contents of which are incorporated by reference.
It will also be appreciated by persons of ordinary skill in the art that the invention is not limited to what has been particularly shown and described hereinabove. For example, drawings or illustrations may not show n or p wells for clarity in illustration. Moreover, transistor channels illustrated or discussed herein may include doped semiconductors, but may instead include undoped semiconductor material. Further, any transferred layer or donor substrate or wafer preparation illustrated or discussed herein may include one or more undoped regions or layers of semiconductor material. Rather, the scope of the invention includes both combinations and sub-combinations of the various features described hereinabove as well as modifications and variations which would occur to such skilled persons upon reading the foregoing description. Thus the invention is to be limited only by the appended claims.
1. A 3D integrated circuit device, comprising:
- a first transistor;
- a second transistor; and
- a third transistor, wherein said third transistor is overlaying said second transistor and is controlled by a third control line, wherein said second transistor is overlaying said first transistor and is controlled by a second control line, wherein said second transistor comprises either a mono-crystal or a polycrystalline channel, wherein said second transistor is a junction-less transistor, wherein said first transistor is part of a control circuit controlling said second control line and third control line, and wherein said first transistor, said second transistor and said third transistor are all aligned to each other with less than 100 nm misalignment.
2. The device according to claim 1,
- wherein said second transistor is self-aligned to said third transistor.
3. The device according to claim 1,
- wherein said third transistor is a part of a third memory cell, said second transistor is a part of a second memory cell and said first transistor is a part of memory periphery circuits controlling said third and second memory cells.
4. The device according to claim 1,
- wherein said second transistor is connected to said third transistor with an ohmic connection.
5. The device according to claim 1,
- wherein at least one of said first transistors is strained for enhanced performance.
6. The device according to claim 1,
- wherein said second transistor comprises a schottky barrier.
7. The device according to claim 1,
- wherein said second transistor comprises a dopant segregated schottky barrier.
8. A 3D integrated circuit device, comprising:
- a first transistor;
- a second transistor; and
- a third transistor, wherein said third transistor is overlaying said second transistor and is controlled by a third control line, wherein said second transistor is overlaying said first transistor and is controlled by a second control line, wherein said second transistor comprises either a mono-crystal or a polycrystalline channel, wherein said second transistor comprises a schottky barrier, and wherein said first transistor, said second transistor and said third transistor are all aligned to each other with less than 100 nm misalignment.
9. The device according to claim 8,
- wherein said second transistor is self-aligned to said third transistor.
10. The device according to claim 8,
- wherein said third transistor is a part of a third memory cell, said second transistor is a part of a second memory cell, and said first transistor is a part of memory periphery circuits controlling said third and second memory cells.
11. The device according to claim 8,
- wherein said second transistor is connected to said third transistor with an ohmic connection.
12. The device according to claim 8,
- wherein said second transistor is a junction-less transistor.
13. The device according to claim 8,
- wherein said first transistor is part of a control circuit controlling said second control line and third control line.
14. The device according to claim 8,
- wherein said second transistor comprises a dopant segregated schottky barrier.
15. A 3D integrated circuit device, comprising:
- a first transistor;
- a first memory cell comprising a second transistor; and
- a second memory cell comprising a third transistor, wherein said third transistor is overlaying said second transistor and said second transistor is overlaying said first transistor, wherein said first transistor is part of a control circuit controlling said first and second memory cell, wherein said second transistor comprises either a mono-crystal or a polycrystalline channel, wherein said second transistor is a junction-less transistor, wherein said first transistor, said second transistor and said third transistor are all aligned to each other with less than 100 nm misalignment, and wherein said second transistor is connected to said third transistor with an ohmic connection.
16. The device according to claim 15,
- wherein said second transistor is self-aligned to said third transistor.
17. The device according to claim 15,
- wherein said third transistor is a part of a third memory cell, said second transistor is a part of a second memory cell and said first transistor is a part of memory periphery circuits controlling said third and second memory cells.
18. The device according to claim 15,
- wherein said second transistor is a junction-less transistor.
19. The device according to claim 15,
- wherein said second transistor comprises a schottky barrier.
20. The device according to claim 1,
- wherein said second transistor comprises a dopant segregated schottky barrier.
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Filed: Mar 7, 2017
Date of Patent: Aug 20, 2019
Patent Publication Number: 20170179155
Assignee: MONOLITHIC 3D INC. (San Jose, CA)
Inventors: Zvi Or-Bach (San Jose, CA), Deepak C. Sekar (San Jose, CA), Brian Cronquist (San Jose, CA)
Primary Examiner: Lynne A Gurley
Assistant Examiner: Vernon P Webb
Application Number: 15/452,615
International Classification: H01L 27/108 (20060101); H01L 21/762 (20060101); H01L 27/06 (20060101); H01L 27/11578 (20170101); H01L 27/24 (20060101); H01L 45/00 (20060101);