Patents by Inventor Brian Cronquist

Brian Cronquist has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR SYSTEM, DEVICE AND STRUCTURE
    Publication number: 20170200715
    Abstract: An Integrated Circuit device, including: first transistors and second transistors, where the first transistors and the second transistors each include a single crystal channel, where at least one of the second transistors overlays at least one of the first transistors with less than 1 micron distance apart, and where at least one of the second transistors is a dopant segregated schottky barrier transistor.
    Type: Application
    Filed: March 27, 2017
    Publication date: July 13, 2017
    Applicant: Monolithic 3D Inc.
    Inventors: Deepak Sekar, Zvi Or-Bach, Brian Cronquist
  • 3D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE
    Publication number: 20170186770
    Abstract: A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor, the memory peripherals transistor is overlaying the second transistor or is underneath the first transistor, where the second memory cell overlays the first memory cell at a distance of less than 200 nm, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.
    Type: Application
    Filed: March 16, 2017
    Publication date: June 29, 2017
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar, Zeev Wurman, Israel Beinglass
  • Semiconductor devices and structures
    Patent number: 9691869
    Abstract: An Integrated Circuit device, including: a first layer including first transistors; and a second layer including second transistors overlaying the first layer, where the first transistors are facing down and the second transistors are facing up, and where the second layer includes a through layer via of less than 300 nm diameter.
    Type: Grant
    Filed: October 11, 2015
    Date of Patent: June 27, 2017
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • 3D MEMORY DEVICE AND STRUCTURE
    Publication number: 20170179155
    Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and is controlled by a third control line, where the second transistor is overlaying the first transistor and is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and third control line, and where the first transistor, the second transistor and the third transistor are all aligned to each other with less than 100 nm misalignment.
    Type: Application
    Filed: March 7, 2017
    Publication date: June 22, 2017
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE
    Publication number: 20170133432
    Abstract: A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor overlaying the second transistor or underneath the first transistor, where the second memory cell overlays the first memory cell, and where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.
    Type: Application
    Filed: January 19, 2017
    Publication date: May 11, 2017
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Zeev Wurman
  • Semiconductor device, structure and methods
    Patent number: 9640531
    Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer overlaying the first layer, the second layer including second transistors, where the second layer includes at least one thru layer via with a diameter less than 200 nm, where the second layer includes an oscillator, and where the oscillator has a frequency stability of less than 100 ppm error/° C.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: May 2, 2017
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • 3D semiconductor device having two layers of transistors
    Patent number: 9613844
    Abstract: A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and overlying the first layer; and a second layer including second transistors, where the second layer thickness is less than 2 microns and greater than 5 nm, where the second layer is overlying the first interconnection layer, and where the second layer includes dice lines formed by an etch step.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: April 4, 2017
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar, Zeev Wurman, Israel Beinglass
  • Semiconductor system, device and structure
    Patent number: 9613887
    Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between at least a portion of the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second transistors, the second layer overlying the at least one metal layer; and at least one conductive structure constructed to provide power to a portion of the second transistors, where the provide power is controlled by at least one of the transistors.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: April 4, 2017
    Assignee: Monolithic 3D Inc.
    Inventors: Deepak Sekar, Zvi Or-Bach, Brian Cronquist
  • 3D SEMICONDUCTOR DEVICE AND STRUCTURE
    Publication number: 20170092541
    Abstract: A 3D semiconductor device including: a first structure including first single crystal transistors; a second structure including second single crystal transistors, the second structure overlaying the first single crystal transistors, where at least one of the second single crystal transistors is at least partially self-aligned to at least one of the first single crystal transistors; and at least one thermal conducting path from at least one of the first single crystal transistors and second single crystal transistors to an external surface of the device.
    Type: Application
    Filed: July 2, 2016
    Publication date: March 30, 2017
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • 3D semiconductor device and structure
    Patent number: 9564432
    Abstract: A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; where the second layer includes at least one through layer via to provide connection between at least one of the second transistors and at least one of the first transistors, where the at least one through layer via has a diameter of less than 200 nm; a first set of external connections underlying the first layer to connect the device to external devices; and a second set of external connections overlying the second layer to connect the device to external devices.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: February 7, 2017
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong
  • SEMICONDUCTOR DEVICE AND STRUCTURE
    Publication number: 20160343774
    Abstract: A semiconductor device, including: a first memory cell including a first transistor; a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor self-aligned to the first transistor; and a plurality of junctionless transistors, where at least one of the junctionless transistors controls access to at least one of the memory cells.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 24, 2016
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Zeev Wurman
  • Semiconductor device and structure
    Patent number: 9460991
    Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer overlying the first transistors and including second transistors; wherein the second layer includes a through layer via with a diameter of less than 150 nm; and a first circuit including at least one of the first transistors, and the first circuit has a first circuit output connected to at least one of the second transistors, wherein the at least one of the second transistors is connected to a device output that is designed to be connected to external devices, and wherein the at least one of the second transistors is substantially larger than the at least one of the first transistors.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: October 4, 2016
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Semiconductor device and structure
    Patent number: 9460978
    Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer overlying the first transistors and including second transistors; wherein the second layer includes a through layer via with a diameter of less than 150 nm; and a Phase-Lock-Loop (PLL) circuit, where the Phase-Lock-Loop (PLL) circuit is connected to at least one input structure, and where the least one input structure is designed to connect an input to the device from external devices.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: October 4, 2016
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • System comprising a semiconductor device and structure
    Patent number: 9406670
    Abstract: A semiconductor device, including: a first layer including first transistors, the first transistors are interconnected by at least one metal layer including copper or aluminum; a second layer including second transistors, the first layer is overlaid by the second layer, where the second layer includes a plurality of through layer vias having a diameter of less than 200 nm, where the second transistors include a source contact, the source contact including a silicide, and where the silicide has a sheet resistance of less than 15 ohm/sq.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: August 2, 2016
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong, Deepak C. Sekar, Zeev Wurman
  • SEMICONDUCTOR SYSTEM, DEVICE AND STRUCTURE
    Publication number: 20160204085
    Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between at least a portion of the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second transistors, the second layer overlying the at least one metal layer; and at least one conductive structure constructed to provide power to a portion of the second transistors, where the provide power is controlled by at least one of the transistors.
    Type: Application
    Filed: March 23, 2016
    Publication date: July 14, 2016
    Applicant: Monolithic 3D Inc.
    Inventors: Deepak Sekar, Zvi Or-Bach, Brian Cronquist
  • Semiconductor device and structure
    Patent number: 9385058
    Abstract: An Integrated Circuit device, including: a base wafer including first electronic circuits and a plurality of first single crystal transistors; at least one metal layer; and a second layer including second electronic circuits and a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; the second layer includes a through layer via with a diameter of less than 150 nm; a portion of the first electronic circuits is circumscribed by a first dice lane, and there are no conductive connections to the portion of the first electronic circuits that cross the first dice lane; wherein a portion of the second electronic circuits is circumscribed by a second dice lane, and there are no conductive connections to the portion of the second electronic circuits that cross the second dice lane, and the second dice lane is overlaying and aligned to the first dice lane.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 5, 2016
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • 3D semiconductor device and structure
    Patent number: 9385088
    Abstract: A semiconductor device including: a first layer including first transistors including at least one first monocrystalline silicon transistor channel; a second layer including second transistors including at least one second monocrystalline non-silicon transistor channel; a plurality of connection paths extending from the second transistors to the first transistors, where at least one of the connection paths includes at least one through layer via with a diameter of less than 200 nm.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: July 5, 2016
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE
    Publication number: 20160141274
    Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a first wire structure constructed to provide power to a portion of the first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and a second wire structure constructed to provide power to a portion of the second transistors, where the second wire structure is isolated from the first wire structure to provide a different power voltage to the portion of the second transistors.
    Type: Application
    Filed: January 28, 2016
    Publication date: May 19, 2016
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • NOVEL SEMICONDUCTOR SYSTEM AND DEVICE
    Publication number: 20160111369
    Abstract: A 3D IC device including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a global power grid to distribute power to the device overlaying the second layer; and a local power grid to distribute power to the first mono-crystallized transistors, where the global power grid is connected to the local power grid by a plurality of through second layer vias, and where the vias have a radius of less than 150 nm.
    Type: Application
    Filed: December 20, 2015
    Publication date: April 21, 2016
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Zeev Wurman
  • Semiconductor devices and structures
    Patent number: 9305867
    Abstract: An Integrated Circuit device including: a first layer including first transistors; a first metal layer overlaying the first transistors and providing at least one connection to the first transistors; a second metal layer overlaying the first metal layer; and a second layer including second transistors overlaying the second metal layer, where the second metal layer is connected to provide power to at least one of the second transistors and a connection path between the second transistors and the second metal layer, where the connection path includes at least one through-layer via, and where the through-layer via has a diameter less than 150 nm.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: April 5, 2016
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist