Patents by Inventor Brian Cronquist

Brian Cronquist has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor system, device and structure with heat removal
    Patent number: 9299641
    Abstract: A 3D device including: a first layer including first transistors, the first layer overlaid by at least one interconnection layer; a second layer including second transistors, the second layer overlaying the interconnection layer; a plurality of electrical connections connecting the second transistors with the interconnection layer; and at least one thermally conductive and electrically non-conductive contact, where the at least one thermally conductive and electrically non-conductive contact thermally connects the second layer to a top or bottom surface of the 3D device.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: March 29, 2016
    Assignee: MONOLITHIC 3D INC.
    Inventors: Deepak Sekar, Zvi Or-Bach, Brian Cronquist
  • SEMICONDUCTOR DEVICES AND STRUCTURES
    Publication number: 20160035722
    Abstract: An Integrated Circuit device, including: a first layer including first transistors; and a second layer including second transistors overlaying the first layer, where the first transistors are facing down and the second transistors are facing up, and where the second layer includes a through layer via of less than 300 nm diameter.
    Type: Application
    Filed: October 11, 2015
    Publication date: February 4, 2016
    Applicant: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Semiconductor device and structure
    Patent number: 9252134
    Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a second layer including a plurality of second transistors, the second layer overlying the at least one metal layer, where the plurality of second transistors include single crystal, and where the second layer includes a through layer via with a diameter of less than 250 nm; a plurality of conductive pads, where at least one of the conductive pads overlays at least one of the second transistors; and at least one I/O circuit, where the at least one I/O circuit is adapted to interface with external devices through at least one of the plurality of conductive pads, where the at least one I/O circuit includes at least one of the first transistors.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: February 2, 2016
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Semiconductor system and device
    Patent number: 9219005
    Abstract: A 3D IC based mobile system including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a plurality of thermal paths between the second mono-crystallized transistors and a heat removal apparatus, where at least one of the plurality of thermal paths includes a thermal contact adapted to conduct heat and not conduct electricity; and a heat spreader layer between the second layer and the at least one metal layer.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: December 22, 2015
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak Sekar, Brian Cronquist, Ze'ev Wurman
  • NOVEL 3D SEMICONDUCTOR DEVICE AND STRUCTURE
    Publication number: 20150348945
    Abstract: A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and overlying the first layer; and a second layer including second transistors, where the second layer thickness is less than 2 microns and greater than 5 nm, where the second layer is overlying the first interconnection layer, and where the second layer includes dice lines formed by an etch step.
    Type: Application
    Filed: August 7, 2015
    Publication date: December 3, 2015
    Applicant: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar, Zeev Wurman, Israel Beinglass
  • NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE
    Publication number: 20150340316
    Abstract: A 3D device, including: a first layer including a first memory including a first transistor; and a second layer including a second memory including a second transistor; where the second transistor is self-aligned to the first transistor, and where the first transistor and the second transistor each being a junction-less transistor.
    Type: Application
    Filed: July 31, 2015
    Publication date: November 26, 2015
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • SEMICONDUCTOR SYSTEM, DEVICE AND STRUCTURE WITH HEAT REMOVAL
    Publication number: 20150311142
    Abstract: A 3D device including: a first layer including first transistors, the first layer overlaid by at least one interconnection layer; a second layer including second transistors, the second layer overlaying the interconnection layer; a plurality of electrical connections connecting the second transistors with the interconnection layer; and at least one thermally conductive and electrically non-conductive contact, where the at least one thermally conductive and electrically non-conductive contact thermally connects the second layer to a top or bottom surface of the 3D device.
    Type: Application
    Filed: June 23, 2015
    Publication date: October 29, 2015
    Applicant: MONOLITHIC 3D INC.
    Inventors: Deepak Sekar, Zvi Or-Bach, Brian Cronquist
  • 3D semiconductor device and structure with back-bias
    Patent number: 9136153
    Abstract: A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and includes aluminum or copper; a second layer including second transistors; where the second transistors are aligned to the first transistors with a less than 40 nm alignment error, and where the second layer is overlying the first interconnection layer, and where at least one of the second transistors has a back-bias structure designed to modify the performance of at least one of the second transistors.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: September 15, 2015
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Ze'ev Wurman, Paul Lim
  • NOVEL 3D SEMICONDUCTOR DEVICE AND STRUCTURE
    Publication number: 20150249053
    Abstract: A semiconductor device including: a first layer including first transistors including at least one first monocrystalline silicon transistor channel; a second layer including second transistors including at least one second monocrystalline non-silicon transistor channel; a plurality of connection paths extending from the second transistors to the first transistors, where at least one of the connection paths includes at least one through layer via with a diameter of less than 200 nm.
    Type: Application
    Filed: February 19, 2015
    Publication date: September 3, 2015
    Applicant: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Semiconductor device and structure
    Patent number: 9117749
    Abstract: A semiconductor device, including: a first transistor sharing a first diffusion with a second transistor; a third transistor sharing a second diffusion with the second transistor; and at least one programmable resistor; wherein the at least one programmable resistor is connected to the first diffusion and the second diffusion, wherein the at least one programmable resistor includes one of the following: memristor, transition metal oxides, polymeric memristor, ferroelectric memristor, spintronic memristor, spin transfer torque, phase-change structure, programmable metallization structure, conductive-bridging structure, magnetoresistive structure, chalcogenide structure.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 25, 2015
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Integrated circuit device and structure
    Patent number: 9099526
    Abstract: A device, including: an integrated circuit chip, where the integrated circuit chip includes: a first layer including a plurality of first transistors including a mono-crystal channel; at least one metal layer overlying the first layer, the at least one metal layer including aluminum or copper and providing interconnection between the first transistors; a second layer overlying the at least one metal layer, the second layer including second horizontally oriented transistors including a second mono-crystal channel; and a through the second layer via of diameter less than 150 nm, where the second horizontally oriented transistors are interconnected to form logic circuits.
    Type: Grant
    Filed: October 2, 2011
    Date of Patent: August 4, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Semiconductor system, device and structure with heat removal
    Patent number: 9099424
    Abstract: A mobile system, including: a 3D device, the 3D device including: a first layer of first transistors, overlaid by at least one interconnection layer, where the interconnection layer comprises copper or aluminum; a second layer including second transistors, the second layer overlaying the interconnection layer, the second layer including: a plurality of electrical connections connecting the second transistors with the interconnection layer; and at least one thermally conductive and electrically non-conductive contact, the at least one thermally conductive and electrically non-conductive contact thermally connects the second layer to the top or bottom surface of the 3D device.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: August 4, 2015
    Assignee: MONOLITHIC 3D INC.
    Inventors: Deepak Sekar, Zvi Or-Bach, Brian Cronquist
  • Method for fabrication of a semiconductor device and structure
    Patent number: 9029173
    Abstract: A method for formation of a semiconductor device, the method including: providing a first mono-crystalline layer including first transistors and first alignment marks; providing an interconnection layer including aluminum or copper on top of the first mono-crystalline layer; and then forming a second mono-crystalline layer on top of the first mono-crystalline layer interconnection layer by using a layer transfer step, and then processing second transistors on the second mono-crystalline layer including a step of forming a gate dielectric, where at least one of the second transistors is a p-type transistor and at least one of the second transistors is an n-type transistor.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: May 12, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Ze'ev Wurman
  • Semiconductor device and structure
    Patent number: 9030858
    Abstract: A semiconductor device, including: a first semiconductor layer including first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; and a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer, wherein the second mono-crystallized semiconductor layer is less than 100 nm in thickness, and wherein the second transistors include horizontally oriented transistors.
    Type: Grant
    Filed: September 23, 2012
    Date of Patent: May 12, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak Sekar, Brian Cronquist, Paul Lim
  • Method of processing a semiconductor device
    Patent number: 9023688
    Abstract: A method for processing a semiconductor device, the method including; providing a first semiconductor layer including first transistors; forming interconnection layers overlying the transistors, where the interconnection layers include copper or aluminum; forming a shielding heat conducting layer overlaying the interconnection layers; forming an isolation layer overlaying the shielding heat conducting layer; forming a second semiconductor layer overlying the isolation layer, and processing the second semiconductor layer at a temperature greater than about 400° C., where the interconnection layers are kept at a temperature below about 400° C.
    Type: Grant
    Filed: June 7, 2014
    Date of Patent: May 5, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Albert Karl Henning
  • Semiconductor device and structure
    Patent number: 9000557
    Abstract: A device including a first layer of first transistors interconnected by at least one first interconnection layer, where the first interconnection layer includes copper or aluminum, a second layer including second transistors, the second layer overlaying the first interconnection layer, where the second layer is less than about 2 micron thick, where the second layer has a coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first interconnection layer, where the connection path includes at least one through-layer via, where the at least one through-layer via is formed through and in direct contact with a source or drain of at least one of the second transistors.
    Type: Grant
    Filed: March 17, 2012
    Date of Patent: April 7, 2015
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE
    Publication number: 20150069523
    Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and at least one conductive structure underneath at least one of the second single crystal transistors, the at least one conductive structure is constructed to provide a back-bias to at least one of the second single crystal transistors.
    Type: Application
    Filed: November 14, 2014
    Publication date: March 12, 2015
    Applicant: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Semiconductor device and structure for heat removal
    Patent number: 8975670
    Abstract: A semiconductor device, including: a semiconductor substrate with a first layer including first transistors; a shield layer overlaying the first layer; a second layer overlaying the shield layer, the second layer including second transistors; wherein the shield layer is a mostly continuous layer with a plurality of regions for connections between the first transistors and the second transistors, and where the second transistors include monocrystalline regions.
    Type: Grant
    Filed: July 22, 2012
    Date of Patent: March 10, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • NOVEL 3D SEMICONDUCTOR DEVICE AND STRUCTURE
    Publication number: 20150061036
    Abstract: A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; at least one contact to the second transistors, where the at least one contact has a diameter of less than 200 nm; a first set of external connections underlying the first layer to connect the device to external devices; a second set of external connections overlying the second layer to connect the device to external devices; and an interconnection layer in-between the first layer and the second layer, where the interconnection layer includes copper or aluminum.
    Type: Application
    Filed: October 8, 2014
    Publication date: March 5, 2015
    Applicant: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong
  • Semiconductor device and structure
    Patent number: 8921970
    Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a second layer including a plurality of second transistors, the second layer overlying the at least one metal layer; where the second layer includes a through layer via with a diameter of less than 150 nm, and where at least one of the second transistors includes a back-bias structure.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: December 30, 2014
    Assignee: Monolithic 3D Inc
    Inventors: Zvi Or-Bach, Brian Cronquist