Abstract: A semiconductor device, including: a first layer including first transistors; an interconnection layer overlying the first transistors, the interconnection layer providing interconnection for the first transistors; a bonding layer overlying the interconnection layer; a second layer overlying the bonding layer; and a carrier substrate for the transferring of the second layer, where the second layer includes at least one through second layer via, where the at least one through second layer via has a diameter of less than 100 nm, where the second layer includes a plurality of second transistors, and where the second layer is transferred from a donor wafer.

Abstract: A semiconductor device comprising power distribution wires wherein; a portion of said wires have thermal connection to the semiconductor layer and said thermal connection designed to conduct heat but to not conduct electricity.

Abstract: An Integrated Circuit device including: a first layer of first transistors; a first metal layer overlaying the first transistors and providing at least one connection to the first transistors; a second metal layer overlaying the first metal layer; and a second layer of second transistors overlaying the second metal layer, where the second metal layer is connected to provide power to at least one of the second transistors.

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer including second transistors; where the second transistors are aligned to the first transistors, and a first circuit including at least one of the first transistors, where the first circuit has a first circuit output connected to at least one of the second transistors, and where at least one of the second transistors is connected to a device output, and where the device output includes a contact port for connection to external devices, and where at least one of the second transistors is substantially larger than at least one of the first transistors.

Abstract: A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.

Abstract: A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, the at least one metal layer overlying the first single crystal layer and includes copper or aluminum; and a second layer overlying the metal layer; the second layer includes second transistors which include mono-crystal and are aligned to the first alignment mark with less than 40 nm alignment error, the mono-crystal includes a first region and second region which are horizontally oriented with respect to each other, the first region has substantially different dopant concentration than the second region.

Abstract: A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, the at least one metal layer overlying the first single crystal layer and includes copper or aluminum; and a second layer overlying the metal layer; the second layer includes second transistors which include mono-crystal and are aligned to the first alignment mark with less than 40 nm alignment error, the mono-crystal includes a first region and second region which are horizontally oriented with respect to each other, the first region has substantially different dopant concentration than the second region.

Abstract: A method of manufacturing semiconductor devices: providing a first device including a first die and second die, where the first die is diced from a first wafer, the second die is diced from a second wafer, the first die is connected to the second die using at least one through-silicon-via; providing a second device including a third die and fourth die, where the third die is diced from a third wafer, the fourth die is diced from a fourth wafer, the third die is connected to the fourth die using at least one through-silicon-via; where the first die includes a first functionality and the third die includes a second functionality, the first functionality is different than the second functionality, a majority of the masks used for processing the first wafer and the third wafer are the same; and the second die size is substantially different than the fourth die size.

Abstract: A method for fabricating a device, the method including: providing a first layer including first transistors, where the first transistors include a mono-crystalline semiconductor; overlaying a second semiconductor layer over the first layer; fabricating a plurality of memory cell control lines where the control lines include a portion of the second layer; where the second layer includes second transistors, where the second transistors include a mono-crystalline semiconductor, and where the second transistors are configured to be memory cells.

Abstract: A device with an external surface, the device including: a substrate including first mono-crystal transistors; a second layer including second mono-crystal transistors, the second mono-crystal transistors overlaying the first mono-crystal transistors; and a plurality of thermal conduction paths from a plurality of the second layer locations to the external surface, wherein at least one of the thermal conduction paths includes an electrically nonconductive contact.

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and at least one conductive layer underneath the second layer, the at least one conductive layer is constructed to provide a back-bias to a portion of the plurality of second single crystal transistors.

Abstract: A method to construct configurable systems, the method including: providing a first configurable system including a first die and a second die, where the connections between the first die and the second die include through-silicon-via (“TSV”), where the first die is diced from a first wafer using first dice lines; providing a second configurable system including a third die and a fourth die, where the connections between the third die and the fourth die include through-silicon-via (“TSV”), where the third die is diced from a third wafer using third dice lines; and processing the first wafer and the third wafer utilizing at least 20 masks that are the same; where the first dice lines are substantially different than the third dice lines, and where the second die includes a configurable I/O to connect the first configurable system to external devices.

Abstract: A computing system including a processor, display, pointing device and memory; wherein the memory includes a text file, a graphics file corresponding to said text file and executable instructions to perform at least these actions (i) identify a selection of an alphanumeric identifier within a displayed text file, and then (ii) identify the appearance of the identifier in a corresponding graphics file, and then (iii) display a page of the graphics file comprising the appearance of the identifier.

Abstract: A method for formation of a semiconductor device including a first wafer including a first single crystal layer comprising first transistors and first alignment mark, the method including: implanting to form a doped layer within a second wafer; forming a second mono-crystalline layer on top of the first wafer by transferring at least a portion of the doped layer using layer transfer step, and completing the formation of second transistors on the second mono-crystalline layer including a step of forming a gate dielectric followed by second transistors gate formation step, wherein the second transistors are horizontally oriented.

Abstract: A 3D memory device, including: a first memory layer including a first memory transistor with side gates; a second memory layer including a second memory transistor with side gates; and a periphery circuits layer including logic transistors for controlling the memory, the periphery circuits are covered by a first isolation layer, where the first memory layer includes a first monolithically mono-crystal layer directly bonded to a second isolation layer, and the second memory layer includes a second monolithically mono-crystal layer directly bonded to the second isolation layer, and the first mono-crystal layer is bonded on top of the first isolation layer, and the second memory transistor is self-aligned to the first memory transistor.

Abstract: A method to form a monolithic 3D device including: processing a first layer including first mono-crystal transistors; transferring a second mono-crystal layer on top of the first layer including first mono-crystal transistors by using ion-cut layer transfer; and repairing the damage caused by the ion-cut by using optical annealing.

Abstract: A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.

Abstract: A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.

Abstract: A semiconductor device including: a first mono-crystal layer and a second mono-crystal layer and at least one conductive layer in-between; where the at least one conductive layer includes a first conductive layer overlaying a second conductive layer overlying a third conductive layer, and where the second conductive layer having a predetermined second layer current carrying capacity greater than the current carrying capacity of the first conductive layer, and the second conductive layer current carrying capacity being greater than the current carrying capacity of the third conductive layer.

Abstract: A device including a first layer of first transistors interconnected by at least one first interconnection layer, wherein the first interconnection layer includes copper or aluminum, a second layer including second transistors, the second layer overlaying the first interconnection layer, wherein the second layer is less than 2 micron thick, wherein the second layer has a coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first interconnection layer, wherein the connection path includes at least one through-layer via, and wherein the through-layer via includes material whose co-efficient of thermal expansion is within 50 percent of the second layer coefficient of thermal expansion.