Abstract: Techniques for tuning the NP boundary between the gate electrode materials of NMOS and PMOS transistors so that the NP boundary is closer to the PMOS transistor can enable the fabrication of a PMOS transistor that is weaker than the adjacent NMOS transistor. In one example, an IC structure includes a first nanoribbon stack and a second nanoribbon stack adjacent to the first nanoribbon stack, a first gate electrode material (e.g., including an N-type work function metal) at least partially around nanoribbons of the first stack and a second gate electrode material (e.g., including a P-type work function metal) at least partially around the nanoribbons of the second stack, where a boundary between the first gate electrode material and the second gate electrode material is closer to the second nanoribbon stack than the first nanoribbon stack.

Abstract: Techniques are provided herein to form an integrated circuit having source and/or drain regions with shaped bottom surfaces to reduce parasitic capacitance. In an example, the bottom portions of the source and/or drain regions may be etched from the backside to form inwardly tapered ends. An array of semiconductor devices each include a semiconductor region extending (e.g., in a first direction) from a source region to a drain region, with a gate structure extending (e.g., in a second direction perpendicular to the first direction) over the semiconductor region. A lower portion of the source and/or drain regions (e.g., a portion at least extending below the semiconductor region) has an inwardly tapered shape. The inward taper may be provided using a backside etching process. The tapered ends of the source and/or drain regions have an increased distance to the adjacent gate structures, thus reducing the parasitic capacitance.

Abstract: The present disclosure relates to the field of firefighter facial masks. More specifically, the present disclosure relates to a firefighter respirator mask device that includes a body, a facial covering over an opening of an SCBA mask, a fastening mechanism and a filter. The body of the device preferably resembles an ovular shape, or any shape that sufficiently covers the hole left over the mouth of an SCBA mask when not attached to an oxygenated hose, normally present under hazardous conditions. The device includes color-changing technology that allows the facial mask to turn colors in response to pathogenic exposure, indicating to the user that it is no longer sterile. In this manner, the device can be applied to any firefighter or industrial worker requiring the use of an SCBA without risk of possible pathogenic exposure when not attached to an oxygenated hose.

Abstract: A transistor structure includes a channel region including first sidewall. A gate electrode includes a first layer having a first portion adjacent to the first sidewall and a second portion adjacent to a gate electrode boundary sidewall. The gate electrode includes a second layer between the first and second portions of the first layer. The first layer has a first composition associated with a first work function material, and has a first lateral thickness from the first sidewall. The second layer has a second composition associated with a second work function material. Depending one a second lateral thickness of the second layer, the second layer may modulate a threshold voltage (VT) of the transistor structure by more or less. In some embodiments, a ratio of the second lateral thickness to the first lateral thickness is less than three.

Abstract: Disclosed are systems and methods that provide a decision-intelligence (DI)-based, computerized framework for automatically and dynamically managing fiber assets within a distributed ledger. The framework operates via predicted insights into how a fiber optic network, inclusive of the fiber assets as a whole and/or individualized, can be optimized to provide accurate, efficient and/or reliable network facilities for associated entities. OTDR data can be utilized by the framework to perform maintenance, troubleshooting and/or to ensure the network operates efficiently. Accordingly the framework can operate to manage, analyze and utilize such forms and/or types of data to curate computerized fiber optic solutions for the fiber optic networks and/or the entities that are operating therefrom, which can be effectuated via the implementation of the disclosed systems and methods within a fiber optics network infrastructure.

Abstract: A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include monocrystalline silicon. An epitaxial source material is coupled to a first end of the first and second channel layers. An epitaxial drain material is coupled to a second end of the first and second channel layers, a gate electrode is between the epitaxial source material and the epitaxial drain material, and around the first channel layer and around the second channel layer. The transistor structure further includes a first gate dielectric layer between the gate electrode and each of the first channel layer and the second channel layer, where the first gate dielectric layer has a first dielectric constant. A second gate dielectric layer is between the first gate dielectric layer and the gate electrode, where the second gate dielectric layer has a second dielectric constant.

Abstract: Techniques are provided herein to form an integrated circuit having source and/or drain regions with shaped bottom surfaces to reduce parasitic capacitance. In an example, the bottom portions of the source and/or drain regions may be etched from the backside to form inwardly tapered ends. An array of semiconductor devices each include a semiconductor region extending (e.g., in a first direction) from a source region to a drain region, with a gate structure extending (e.g., in a second direction perpendicular to the first direction) over the semiconductor region. A lower portion of the source and/or drain regions (e.g., a portion at least extending below the semiconductor region) has an inwardly tapered shape. The inward taper may be provided using a backside etching process. The tapered ends of the source and/or drain regions have an increased distance to the adjacent gate structures, thus reducing the parasitic capacitance.

Abstract: An integrated circuit includes a first source region, a first drain region, a first fin having (i) a first upper region laterally between the first source region and the first drain region and (ii) a first lower region below the first upper region, and a first gate structure on at least top and side surfaces of the first upper region. The integrated circuit further includes a second source region, a second drain region, a second fin having (i) a second upper region laterally between the second source region and the second drain region and (ii) a second lower region below the second upper region, and a second gate structure on at least top and side surfaces of the second upper region. In an example, a first vertical height of the first lower region is different from a second vertical height of the second lower region by at least 2 nanometers (nm).

Abstract: Substrate-less lateral diode integrated circuit structures, and methods of fabricating substrate-less lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin or a stack of nanowires. A plurality of P-type epitaxial structures is over the fin or stack of nanowires. A plurality of N-type epitaxial structures is over the fin or stack of nanowires. One or more spacings are in locations over the fin or stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

Abstract: Embodiments of the present disclosure include integrated circuit structures having differentiated channel sizing, and methods of fabricating integrated circuit structures having differentiated channel sizing. In an example, a structure includes a memory region having a first vertical stack of horizontal nanowires having a first number of nanowires. The integrated circuit structure also includes a logic region having a second vertical stack of horizontal nanowires spaced apart from the first vertical stack of horizontal nanowires. The second vertical stack of horizontal nanowires has a second number of nanowires less than the first number of nanowires.

Abstract: Integrated circuitry comprising high voltage (HV) and low voltage (LV) ribbon or wire (RoW) transistor stack structures. In some examples, a gate electrode of the HV and LV transistor stack structures may include the same work function metal. A metal oxide may be deposited around one or more channels of the HV transistor stack, thereby altering the dipole properties of the gate insulator stack from those of the LV transistor stack structure.

Abstract: Fabrication methods that employ an etch stop layer to assist subfin removal during fabrication of nanoribbon-based transistors are disclosed. An example fabrication method includes providing a stack of nanoribbons above a subfin, where the nanoribbons and the subfin include one or more semiconductor materials; depositing an etch stop layer over a top of the subfin and around portions of the nanoribbons; removing the etch stop layer from around the portions of the nanoribbons; providing a gate dielectric material around the portions of the nanoribbons and over the etch stop layer over the top of the subfin; depositing a gate electrode material around the portions of the nanoribbons; and performing an etch to remove the subfin without substantially removing the etch stop layer.

Abstract: Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.

Abstract: Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures.

Abstract: Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.

Abstract: Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures.

Abstract: Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal.

Abstract: Substrate-less vertical diode integrated circuit structures, and methods of fabricating substrate-less vertical diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor fin in a dielectric layer, the semiconductor fin having a top and a bottom, and the dielectric layer having a top surface and a bottom surface. A first epitaxial semiconductor structure is on the top of the semiconductor fin. A second epitaxial semiconductor structure is on the bottom of the semiconductor fin. A first conductive contact is on the first epitaxial semiconductor structure. A second conductive contact is on the second epitaxial semiconductor structure.

Abstract: An apparatus comprising a source or drain of a field effect transistor (FET), a first dielectric between a portion of the source or drain and a FET gate, the first dielectric comprising silicon nitride, and a second dielectric above at least a portion of the first dielectric, the second dielectric comprising silicon oxide doped with at least one of oxygen or carbon, the second dielectric having a dielectric constant lower than the first dielectric.

Abstract: Fabrication methods that employ an etch stop layer to assist subfin removal during fabrication of nanoribbon-based transistors are disclosed. An example fabrication method includes providing a stack of nanoribbons above a subfin, where the nanoribbons and the subfin include one or more semiconductor materials; depositing an etch stop layer over a top of the subfin and around portions of the nanoribbons; removing the etch stop layer from around the portions of the nanoribbons; providing a gate dielectric material around the portions of the nanoribbons and over the etch stop layer over the top of the subfin; depositing a gate electrode material around the portions of the nanoribbons; and performing an etch to remove the subfin without substantially removing the etch stop layer.