Patents by Inventor Brian Greene
Brian Greene has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210408289Abstract: A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include monocrystalline silicon. An epitaxial source material is coupled to a first end of the first and second channel layers. An epitaxial drain material is coupled to a second end of the first and second channel layers, a gate electrode is between the epitaxial source material and the epitaxial drain material, and around the first channel layer and around the second channel layer. The transistor structure further includes a first gate dielectric layer between the gate electrode and each of the first channel layer and the second channel layer, where the first gate dielectric layer has a first dielectric constant. A second gate dielectric layer is between the first gate dielectric layer and the gate electrode, where the second gate dielectric layer has a second dielectric constant.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Applicant: Intel CorporationInventors: Biswajeet Guha, Brian Greene, Robin Chao, Adam Faust, Chung-Hsun Lin, Curtis Tsai, Kevin Fischer
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Publication number: 20210305436Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.Type: ApplicationFiled: March 25, 2020Publication date: September 30, 2021Inventors: Ayan KAR, Saurabh MORARKA, Carlos NIEVA-LOZANO, Kalyan KOLLURU, Biswajeet GUHA, Chung-Hsun LIN, Brian GREENE, Tahir GHANI
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Patent number: 10867912Abstract: Structures that include a passive device, such as a metal-based resistor, and methods of forming a structure that includes a passive device. The structure includes a semiconductor substrate, an interconnect structure including a passive device, and a dummy fill region arranged between the passive device and the semiconductor substrate. The dummy fill region includes a plurality of shallow trench isolation regions in the semiconductor substrate, a plurality of semiconductor fins, a plurality of source/drain regions in the plurality of semiconductor fins, and a plurality of contacts arranged over the plurality of shallow trench isolation regions.Type: GrantFiled: January 15, 2019Date of Patent: December 15, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Jaladhi Mehta, Brian Greene, Daniel J. Dechene, Ahmed Hassan
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Patent number: 10796973Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.Type: GrantFiled: May 29, 2019Date of Patent: October 6, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Mankyu Yang, Vara Govindeswara Reddy Vakada, Edward Maciejewski, Brian Greene, Atsushi Ogino, Vikrant Chauhan, Prianka Sengupta
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Patent number: 10790204Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a test pad, a device-under-testing having one or more source/drain regions, and a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines that are connected with the test pad. One or more contacts, which are arranged between the metallization level and the device-under-testing, directly connect the one or more interconnect lines with the one or more source/drain regions.Type: GrantFiled: November 9, 2018Date of Patent: September 29, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Mankyu Yang, Vara Govindeswara Reddy Vakada, Edward Maciejewski, Brian Greene, Atsushi Ogino, Vikrant Chauhan, Prianka Sengupta
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Publication number: 20200227350Abstract: Structures that include a passive device, such as a metal-based resistor, and methods of forming a structure that includes a passive device. The structure includes a semiconductor substrate, an interconnect structure including a passive device, and a dummy fill region arranged between the passive device and the semiconductor substrate. The dummy fill region includes a plurality of shallow trench isolation regions in the semiconductor substrate, a plurality of semiconductor fins, a plurality of source/drain regions in the plurality of semiconductor fins, and a plurality of contacts arranged over the plurality of shallow trench isolation regions.Type: ApplicationFiled: January 15, 2019Publication date: July 16, 2020Inventors: Jaladhi Mehta, Brian Greene, Daniel J. Dechene, Ahmed Hassan
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Publication number: 20200152531Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.Type: ApplicationFiled: May 29, 2019Publication date: May 14, 2020Inventors: Mankyu Yang, Vara Govindeswara Reddy Vakada, Edward Maciejewski, Brian Greene, Atsushi Ogino, Vikrant Chauhan, Prianka Sengupta
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Publication number: 20200152530Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a test pad, a device-under-testing having one or more source/drain regions, and a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines that are connected with the test pad. One or more contacts, which are arranged between the metallization level and the device-under-testing, directly connect the one or more interconnect lines with the one or more source/drain regions.Type: ApplicationFiled: November 9, 2018Publication date: May 14, 2020Inventors: Mankyu Yang, Vara Govindeswara Reddy Vakada, Edward Maciejewski, Brian Greene, Atsushi Ogino, Vikrant Chauhan, Prianka Sengupta
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Patent number: 10566411Abstract: Device structures and fabrication methods for an on-chip resistor. A resistor body is formed on an interlayer dielectric layer of a contact level. A contact is formed that extends vertically through the interlayer dielectric layer. One or more dielectric layers are formed over the contact level, and a metal feature is formed in the one or more dielectric layers. The metal feature is at least in part in direct contact with a portion of the resistor body.Type: GrantFiled: December 7, 2017Date of Patent: February 18, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Atsushi Ogino, Lin Hu, Brian Greene
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Publication number: 20190181215Abstract: Device structures and fabrication methods for an on-chip resistor. A resistor body is formed on an interlayer dielectric layer of a contact level. A contact is formed that extends vertically through the interlayer dielectric layer. One or more dielectric layers are formed over the contact level, and a metal feature is formed in the one or more dielectric layers. The metal feature is at least in part in direct contact with a portion of the resistor body.Type: ApplicationFiled: December 7, 2017Publication date: June 13, 2019Inventors: Atsushi Ogino, Lin Hu, Brian Greene
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Patent number: 10269932Abstract: One illustrative method disclosed herein includes, among other things, forming a first fin having first and second opposing sidewalls and forming a first sidewall spacer positioned adjacent the first sidewall and a second sidewall spacer positioned adjacent the second sidewall, wherein the first sidewall spacer has a greater height than the second sidewall spacer. In this example, the method further includes forming epitaxial semiconductor material on the fin and above the first and second sidewall spacers.Type: GrantFiled: January 18, 2018Date of Patent: April 23, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Ankur Arya, Brian Greene, Qun Gao, Christopher Nassar, Junsic Hong, Vishal Chhabra
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Patent number: 9780002Abstract: Methodologies for patterning and implantation are provided Embodiments include forming fins; forming an SiN over the fins; forming an a-Si layer over the SiN; forming and patterning a first patterning layer over the a-Si layer; etching through the a-Si layer using the first patterning layer as a mask; removing the first patterning layer; implanting ions in exposed groups of fins; forming and patterning a second patterning layer to expose a first group of fins and a portion of the a-Si layer on opposite sides of the first group of fins; implanting ions in a first region of the first group of fins; forming a third patterning layer over the first region of the first group of fins and exposing a second region of the first group of fins; and implanting ions in the second region of the first group of fins.Type: GrantFiled: June 6, 2016Date of Patent: October 3, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Xintuo Dai, Brian Greene, Mahender Kumar, Daniel J. Dechene, Daniel Jaeger
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Publication number: 20150363710Abstract: Systems and methods for tracking a device are disclosed. The system comprises an identification plate coupled to the device and laser engraved with a tracking identifier, the identification plate adapted to maintain the engraving under stress, elevated temperature, and wear conditions, and at least one computer adapted to read the tracking number and determine the location of the device.Type: ApplicationFiled: June 11, 2014Publication date: December 17, 2015Inventors: Gilbert Troy Meier, James D. Osterloh, Joshua J. Smith, David Gale, Aaron Anderson, Brian Greene, Taylor Sorensen
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Patent number: 7657582Abstract: A system for using recent activity information to select backup versions of storage objects for restoration comprises a processor and memory coupled to the processor, where the memory stores program instructions computer-executable by the processor to implement a backup manager. The backup manager is configured to maintain one or more backup versions of a plurality of storage objects and a plurality of access history records, where each access history record is associated with a particular backup version. Each access history record includes information indicative of an access to the corresponding storage object by a user. The backup manager may be configured to select a particular backup version as a restoration candidate using at least the contents of the access history record associated with the backup version.Type: GrantFiled: August 4, 2005Date of Patent: February 2, 2010Assignee: Symantec Operating CorporationInventors: Paul Cram, Stephen Andrew Breidbach, Anthony T. Orling, Brian Greene
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Publication number: 20090084601Abstract: An electrical receptacle includes an outlet that is protected from the environment in which the receptacle is used. The receptacle is designed for below grade use, such as in a tree well for providing tree lighting or other application in which a dry, clean environment is required. The plug end of a detachable power cord is inserted into the outlet of the receptacle, with foam or similar material being used to maintain the weatherproof condition as the cord exits from the receptacle. The receptacle is prewired for connection to a source of power via a raceway, but Ground Fault Interrupter (GFI) protection breaks the connection from the power source to the cord that is inserted into the outlet, if an unsafe condition is detected.Type: ApplicationFiled: August 25, 2008Publication date: April 2, 2009Inventors: Mike Masinter, Brian Greene
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Publication number: 20070254464Abstract: A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.Type: ApplicationFiled: April 28, 2006Publication date: November 1, 2007Applicant: International Business Machines CorporationInventors: Brian Greene, Louis Hsu, Jack Mandelman, Chun-Yung Sung
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Publication number: 20070249126Abstract: A structure and method for fabricating a transistor structure is provided. The method comprises the steps of: (a) providing a substrate including a semiconductor-on-insulator (“SOI”) layer separated from a bulk region of the substrate by a buried dielectric layer. (b) first implanting the SOI layer to achieve a predetermined dopant concentration at an interface of the SOI layer to the buried dielectric layer. and (c) second implanting said SOI layer to achieve predetermined dopant concentrations in a polycrystalline semiconductor gate conductor (“poly gate”) and in source and drain regions disposed adjacent to the poly gate, wherein a maximum depth of the first implanting is greater than a maximum depth of the second implanting.Type: ApplicationFiled: April 21, 2006Publication date: October 25, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dureseti Chidambarrao, Brian Greene, John Ellis-Monaghan
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Publication number: 20070249131Abstract: An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.Type: ApplicationFiled: April 21, 2006Publication date: October 25, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Scott Allen, Cyril Cabral, Kevin Dezfulian, Sunfei Fang, Brian Greene, Rajarao Jammy, Christian Lavoie, Zhijiong Luo, Hung Ng, Chun-Yung Sung, Clement Wann, Huilong Zhu
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Publication number: 20070173003Abstract: Integrated circuits are oriented on a substrate at an angle that is rotated between 5 to 40 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by adjusting the angle of rotation of the substrate. For a rotated substrate CMOS device design, other stress control measures may be used, such as a stress control or tensile liner, over an NMOS transistor, PMOS transistor, or both, to further adjust the stress and improve performance.Type: ApplicationFiled: February 23, 2007Publication date: July 26, 2007Inventors: Matthias Hierlemann, Chun-Yung Sung, Brian Greene, Manfred Eller
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Publication number: 20070164358Abstract: A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.Type: ApplicationFiled: January 17, 2006Publication date: July 19, 2007Applicant: International Business Machines CorporationInventors: Joel de Souza, Keith Fogel, Brian Greene, Devendra Sadana, Haining Yang