Patents by Inventor Brian J. Campbell
Brian J. Campbell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8289785Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.Type: GrantFiled: June 7, 2011Date of Patent: October 16, 2012Assignee: Apple Inc.Inventors: Brian J. Campbell, Vincent R. von Kaenel, Daniel C. Murray, Gregory S. Scott, Sribalan Santhanam
-
Patent number: 8286987Abstract: An animated novelty device for mounting on a ball of a trailer hitch on a vehicle, the device including an electric motor for imparting motion to selected elements of the device. The motor is electrically connected to the vehicle braking system whereby the device is set in motion by energizing the vehicle brakes.Type: GrantFiled: December 27, 2011Date of Patent: October 16, 2012Assignee: Evoke Ventures, LLCInventors: Brian J. Campbell, Daniel J. Chesnicka, Mark J. McIntyre
-
Publication number: 20120257469Abstract: In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, including one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by a control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion.Type: ApplicationFiled: May 17, 2012Publication date: October 11, 2012Inventors: Brian J. Campbell, Greg M. Hess, Hang Huang
-
Patent number: 8219755Abstract: In one embodiment, a cache comprises a tag memory and a comparator. The tag memory is configured to store tags of cache blocks stored in the cache, and is configured to output at least one tag responsive to an index corresponding to an input address. The comparator is coupled to receive the tag and a tag portion of the input address, and is configured to compare the tag to the tag portion to generate a hit/miss indication. The comparator comprises dynamic circuitry, and is coupled to receive a control signal which, when asserted, is defined to force a first result on the hit/miss indication independent of whether or not the tag portion matches the tag. The comparator also comprises circuitry coupled to receive the control signal and configured to inhibit a state change on an output of the dynamic circuitry during an evaluate phase of the dynamic circuitry to produce the first result responsive to an assertion of the control signal.Type: GrantFiled: August 1, 2011Date of Patent: July 10, 2012Assignee: Apple Inc.Inventor: Brian J. Campbell
-
Publication number: 20120151810Abstract: An animated novelty device for mounting on a ball of a trailer hitch on a vehicle, the device including an electric motor for imparting motion to selected elements of the device. The motor is electrically connected to the vehicle braking system whereby the device is set in motion by energizing the vehicle brakes.Type: ApplicationFiled: December 27, 2011Publication date: June 21, 2012Inventors: Brian J. Campbell, Daniel J. Chesnicka, Mark J. McIntyre
-
Patent number: 8203898Abstract: In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by an input control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled to float the bit lines. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion.Type: GrantFiled: June 29, 2011Date of Patent: June 19, 2012Assignee: Apple Inc.Inventors: Brian J. Campbell, Greg M. Hess, Hang Huang
-
Patent number: 8171326Abstract: In one embodiment, a processor comprises a data cache configured to store a plurality of cache blocks and a control unit coupled to the data cache. The control unit is configured to flush the plurality of cache blocks from the data cache responsive to an indication that the processor is to transition to a low power state in which one or more clocks for the processor are inhibited.Type: GrantFiled: May 24, 2010Date of Patent: May 1, 2012Assignee: Apple Inc.Inventors: James B. Keller, Tse-Yu Yeh, Ramesh Gunna, Brian J. Campbell
-
Patent number: 8102728Abstract: In one embodiment, a memory circuit includes one or more memory cells that include transistors having a first nominal threshold voltage, and interface circuitry such as word line drivers and bit line control circuitry that includes one or more transistors having a second nominal threshold voltage that is lower than the first nominal threshold voltage. For example, the word line driver circuit may be driven by signals from a lower voltage domain than the memory circuit's voltage domain. Lower threshold voltage transistors may be used for those signals, in some embodiments. Similarly, lower threshold voltage transistors may be used in the write data driver circuits. Other bit line control circuits may include lower threshold voltage transistors to permit smaller transistors to be used, which may reduce power and integrated circuit area occupied by the memory circuits.Type: GrantFiled: April 7, 2009Date of Patent: January 24, 2012Assignee: Apple Inc.Inventors: Brian J. Campbell, Greg M. Hess, Hang Huang
-
Patent number: 8098534Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.Type: GrantFiled: June 1, 2010Date of Patent: January 17, 2012Assignee: Apple Inc.Inventors: Brian J. Campbell, Vincent R. von Kaenel, Daniel C. Murray, Gregory S. Scott, Sribalan Santhanam
-
Patent number: 8091915Abstract: An animated novelty device for mounting on a ball of a trailer hitch on a vehicle, the device including an electric motor for imparting motion to selected elements of the device. The motor is electrically connected to the vehicle braking system whereby the device is set in motion by energizing the vehicle brakes.Type: GrantFiled: April 11, 2007Date of Patent: January 10, 2012Assignee: Evoke Ventures, LLCInventors: Brian J. Campbell, Daniel J. Chesnicka, Mark J. McIntyre
-
Publication number: 20110289275Abstract: In one embodiment, a cache comprises a tag memory and a comparator. The tag memory is configured to store tags of cache blocks stored in the cache, and is configured to output at least one tag responsive to an index corresponding to an input address. The comparator is coupled to receive the tag and a tag portion of the input address, and is configured to compare the tag to the tag portion to generate a hit/miss indication. The comparator comprises dynamic circuitry, and is coupled to receive a control signal which, when asserted, is defined to force a first result on the hit/miss indication independent of whether or not the tag portion matches the tag. The comparator also comprises circuitry coupled to receive the control signal and configured to inhibit a state change on an output of the dynamic circuitry during an evaluate phase of the dynamic circuitry to produce the first result responsive to an assertion of the control signal.Type: ApplicationFiled: August 1, 2011Publication date: November 24, 2011Inventor: Brian J. Campbell
-
Publication number: 20110255351Abstract: In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations.Type: ApplicationFiled: June 29, 2011Publication date: October 20, 2011Inventors: Brian J. Campbell, Vincent R. von Kaenel, Naveen Javarappa, Greg M. Hess
-
Publication number: 20110255355Abstract: In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by an input control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled to float the bit lines. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion.Type: ApplicationFiled: June 29, 2011Publication date: October 20, 2011Inventors: Brian J. Campbell, Greg M. Hess, Hang Huang
-
Publication number: 20110235442Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.Type: ApplicationFiled: June 7, 2011Publication date: September 29, 2011Inventors: Brian J. Campbell, Vincent R. von Kaenel, Daniel C. Murray, Gregory S. Scott, Sribalan Santhanam
-
Patent number: 8015356Abstract: In one embodiment, a cache comprises a tag memory and a comparator. The tag memory is configured to store tags of cache blocks stored in the cache, and is configured to output at least one tag responsive to an index corresponding to an input address. The comparator is coupled to receive the tag and a tag portion of the input address, and is configured to compare the tag to the tag portion to generate a hit/miss indication. The comparator comprises dynamic circuitry, and is coupled to receive a control signal which, when asserted, is defined to force a first result on the hit/miss indication independent of whether or not the tag portion matches the tag. The comparator also comprises circuitry coupled to receive the control signal and configured to inhibit a state change on an output of the dynamic circuitry during an evaluate phase of the dynamic circuitry to produce the first result responsive to an assertion of the control signal.Type: GrantFiled: July 1, 2005Date of Patent: September 6, 2011Assignee: Apple Inc.Inventor: Brian J. Campbell
-
Patent number: 7994820Abstract: In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations.Type: GrantFiled: October 20, 2010Date of Patent: August 9, 2011Assignee: Apple Inc.Inventors: Brian J. Campbell, Vincent R. von Kaenel, Naveen Javarappa, Greg M. Hess
-
Patent number: 7995410Abstract: In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by an input control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled to float the bit lines. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion.Type: GrantFiled: June 26, 2009Date of Patent: August 9, 2011Assignee: Apple Inc.Inventors: Brian J. Campbell, Greg M. Hess, Hang Huang
-
Patent number: 7915920Abstract: In one embodiment, an apparatus comprises a circuit supplied by a first supply voltage during use, the circuit having at least a first input signal; and a level shifter supplied by the first supply voltage during use and coupled to provide the first input signal to the circuit. The level shifter is coupled to receive a second input signal sourced from circuitry supplied by a second supply voltage during use, and is configured to generate the first input signal by level shifting the second input signal. Coupled to receive a power control signal indicating, when asserted, that the second supply voltage is to be powered down, the level shifter is configured to assert a predetermined level on the first input signal independent of the second input signal and responsive to an assertion of the power control signal.Type: GrantFiled: December 10, 2009Date of Patent: March 29, 2011Assignee: Apple Inc.Inventors: Brian J. Campbell, Vincent R. von Kaenel
-
Publication number: 20110032020Abstract: In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations.Type: ApplicationFiled: October 20, 2010Publication date: February 10, 2011Inventors: Brian J. Campbell, Vincent R. von Kaenel, Naveen Javarappa, Greg M. Hess
-
Publication number: 20100329062Abstract: In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by an input control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled to float the bit lines. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion.Type: ApplicationFiled: June 26, 2009Publication date: December 30, 2010Inventors: Brian J. Campbell, Greg M. Hess, Hang Huang