Patents by Inventor Brian J. Greene

Brian J. Greene has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7358551
    Abstract: The present invention provides a technique for forming a CMOS structure including at least one pFET that has a stressed channel which avoids the problems mentioned in the prior art. Specifically, the present invention provides a method for avoiding formation of deep canyons at the interface between the active area and the trench isolation region, without requiring a trench isolation pulldown, thereby eliminating the problems of silicide to source/drain shorts and contact issues. At the same time, the method of the present invention provides a structure that allows for a facet to form at the spacer edge, retaining the Miller capacitance benefit that such a structure provides. The inventive structure also results in higher uniaxial stress in the MOSFET channel compared to one which allows for a facet to grow at the trench isolation edge.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: April 15, 2008
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Brian J. Greene
  • Publication number: 20080057653
    Abstract: A method and semiconductor structure that overcome the dual stress liner boundary problem, without significantly increasing the overall size of the integrated circuit, are provided. In accordance with the present invention, the dual stress liner boundary or gap therebetween is forced to land on a neighboring dummy gate region. By forcing the dual stress liner boundary or gap between the liners to land on the dummy gate region, the large stresses associated with the dual stress liner boundary or gap are transferred to the dummy gate region, not the semiconductor substrate. Thus, the impact of the dual stress liner boundary on the nearest neighboring FET is reduced. Additionally, benefits of device variability and packing density are achieved utilizing the present invention.
    Type: Application
    Filed: August 30, 2006
    Publication date: March 6, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dureseti Chidambarrao, Brian J. Greene
  • Patent number: 7317204
    Abstract: A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: January 8, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-chul Sun, Ja-hum Ku, Brian J. Greene, Manfred Eller, Wee Lang Tan, Sunfei Fang, Zhijiong Luo
  • Publication number: 20070161244
    Abstract: A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.
    Type: Application
    Filed: November 22, 2005
    Publication date: July 12, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian J. Greene, Chung Woh Lai, Yong Meng Lee, Wenhe Lin, Siddhartha Panda, Kern Rim, Young Way Teh
  • Patent number: 7205639
    Abstract: Integrated circuits are oriented on a substrate at an angle that is rotated between 0 to 45 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by adjusting the angle of rotation of the substrate. For a rotated substrate CMOS device design, other stress control measures may be used, such as a stress control or tensile liner, over an NMOS transistor, PMOS transistor, or both, to further adjust the stress and improve performance.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: April 17, 2007
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Matthias Hierlemann, Chun-Yung Sung, Brian J. Greene, Manfred Eller