Abstract: A method of forming a self-aligned well implant for a transistor includes forming a patterned gate structure over a substrate, including a gate conductor, a gate dielectric layer and sidewall spacers, the substrate including an undoped semiconductor layer beneath the gate dielectric layer and a doped semiconductor layer beneath the undoped semiconductor layer; removing portions of the undoped semiconductor layer and the doped semiconductor layer left unprotected by the patterned gate structure, wherein a remaining portion of the undoped semiconductor layer beneath the patterned gate structure defines a transistor channel and a remaining portion of the doped semiconductor layer beneath the patterned gate structure defines the self-aligned well implant; and growing a new semiconductor layer at locations corresponding to the removed portions of the undoped semiconductor layer and the doped semiconductor layer, the new semiconductor layer corresponding to source and drain regions of the transistor.

Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

Abstract: A field effect structure and a method for fabricating the field effect structure include a germanium containing channel interposed between a plurality of source and drain regions. The germanium containing channel is coplanar with the plurality of source and drain regions, and the germanium containing channel includes a germanium containing material having a germanium content greater than the germanium content of the plurality of source and drain regions.

Abstract: Threshold voltage controlled semiconductor structures are provided in which a conformal nitride-containing liner is located on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.

Abstract: A transistor device includes a patterned gate structure formed over a substrate, the patterned gate structure including a gate conductor, a gate dielectric layer and sidewall spacers; and a doped well implant formed in the substrate, the well implant being self-aligned with the patterned gate structure.

Abstract: A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

Abstract: A method of forming a transistor device includes implanting a diffusion inhibiting species in a semiconductor-on-insulator substrate comprising a bulk substrate, a buried insulator layer, and a semiconductor-on-insulator layer, the semiconductor-on-insulator substrate having one or more gate structures formed thereon such that the diffusion inhibiting species is disposed in portions of the semiconductor-on-insulator layer corresponding to a channel region, and disposed in portions of the buried insulator layer corresponding to source and drain regions. A transistor dopant species is introduced in the source and drain regions. An anneal is performed so as to diffuse the transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the transistor dopant species into the channel region.

Abstract: A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.

Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

Abstract: A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

Abstract: Disclosed are embodiments of a field effect transistor (FET) having decreased drive current temperature sensitivity. Specifically, any temperature-dependent carrier mobility change in the FET channel region is simultaneously counteracted by an opposite strain-dependent carrier mobility change to ensure that drive current remains approximately constant or at least within a predetermined range in response to temperature variations. This opposite strain-dependent carrier mobility change is provided by a straining structure that is configured to impart a temperature-dependent amount of a pre-selected strain type on the channel region. Also disclosed are embodiments of an associated method of forming the field effect transistor.

Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

Abstract: An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

Abstract: Disclosed are embodiments of a field effect transistor (FET) having decreased drive current temperature sensitivity. Specifically, any temperature-dependent carrier mobility change in the FET channel region is simultaneously counteracted by an opposite strain-dependent carrier mobility change to ensure that drive current remains approximately constant or at least within a predetermined range in response to temperature variations. This opposite strain-dependent carrier mobility change is provided by a straining structure that is configured to impart a temperature-dependent amount of a pre-selected strain type on the channel region. Also disclosed are embodiments of an associated method of forming the field effect transistor.

Abstract: A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses.

Abstract: A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses.

Abstract: A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.

Abstract: A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor.

Abstract: A method of forming a self-aligned well implant for a transistor includes forming a patterned gate structure over a substrate, including a gate conductor, a gate dielectric layer and sidewall spacers, the substrate including an undoped semiconductor layer beneath the gate dielectric layer and a doped semiconductor layer beneath the undoped semiconductor layer; removing portions of the undoped semiconductor layer and the doped semiconductor layer left unprotected by the patterned gate structure, wherein a remaining portion of the undoped semiconductor layer beneath the patterned gate structure defines a transistor channel and a remaining portion of the doped semiconductor layer beneath the patterned gate structure defines the self-aligned well implant; and growing a new semiconductor layer at locations corresponding to the removed portions of the undoped semiconductor layer and the doped semiconductor layer, the new semiconductor layer corresponding to source and drain regions of the transistor.