Patents by Inventor Brian Li

Brian Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230283093
    Abstract: An electrical apparatus comprising a first housing portion and a second housing portion, a first set of battery contacts and a second set of battery contacts, when the second housing portion is at a first relative position, the second set of battery contacts is at an actuation position; and when the second housing portion is at a second relative position, the second set of battery contacts is at a non-actuation position.
    Type: Application
    Filed: May 15, 2023
    Publication date: September 7, 2023
    Inventors: Yiu Cheung Brian Li, Yat Ming Wong, Yui Ho Chan, De Qing Zeng
  • Patent number: 11455373
    Abstract: The present disclosure describes a system, method, and computer program for real-time and computationally efficient calculation of a recommended value range for a quote variable, such as price, discount, volume, or closing time. The system uses the highest-density interval (HDI) of probability density function (PDF) as a recommended or suggested value range for a quote variable. PDFs for the quote variable are precomputed for groups of related inputs, and each PDF is summarized as an array of discrete points. A dimension reduction technique is applied to the PDF inputs in both the training and real-time (non-training) phases to reduce the number of possible combinations of PDFs. During a quote-creation process, a PDF look-up table enables the system to efficiently identify an applicable PDF from the group of precomputed PDFs based on reduced input values.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: September 27, 2022
    Assignee: Apttus Corporation
    Inventors: Kirk G. Krappé, Neehar Giri, Man Chan, Isabelle Chai, Rahul Choudhry, Kitae Kim, Stanley Poon, Brian Li, Geeta Deodhar, Elliott Yama
  • Publication number: 20210088404
    Abstract: A leak inhibition/detection device includes an absorbent material, a leak sensor in contact with the absorbent material, and an enclosure surrounding the absorbent material. The leak inhibition/detection device is configured to surround a joint between tubing and a cold plate/evaporator or a radiator/condenser of a liquid cooling module of an information handling system.
    Type: Application
    Filed: September 25, 2019
    Publication date: March 25, 2021
    Inventors: Chao Hung (Brian) Li, Wen Hung (Steven) Lu
  • Publication number: 20200065354
    Abstract: The present disclosure describes a system, method, and computer program for real-time and computationally efficient calculation of a recommended value range for a quote variable, such as price, discount, volume, or closing time. The system uses the highest-density interval (HDI) of probability density function (PDF) as a recommended or suggested value range for a quote variable. PDFs for the quote variable are precomputed for groups of related inputs, and each PDF is summarized as an array of discrete points. A dimension reduction technique is applied to the PDF inputs in both the training and real-time (non-training) phases to reduce the number of possible combinations of PDFs. During a quote-creation process, a PDF look-up table enables the system to efficiently identify an applicable PDF from the group of precomputed PDFs based on reduced input values.
    Type: Application
    Filed: October 31, 2019
    Publication date: February 27, 2020
    Inventors: Kirk G. Krappé, Neehar Giri, Man Chan, Isabelle Chai, Rahul Choudhry, Kitae Kim, Stanley Poon, Brian Li, Geeta Deodhar, Elliott Yama
  • Patent number: 10521491
    Abstract: The present disclosure describes a system, method, and computer program for real-time and computationally efficient calculation of a recommended value range for a quote variable, such as price, discount, volume, or closing time. The system uses the highest-density interval (HDI) of probability density function (PDF) as a recommended or suggested value range for a quote variable. PDFs for the quote variable are precomputed for groups of related inputs, and each PDF is summarized as an array of discrete points. A dimension reduction technique is applied to the PDF inputs in both the training and real-time (non-training) phases to reduce the number of possible combinations of PDFs. During a quote-creation process, a PDF look-up table enables the system to efficiently identify an applicable PDF from the group of precomputed PDFs based on reduced input values.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: December 31, 2019
    Assignee: Apttus Corporation
    Inventors: Kirk G. Krappé, Neehar Giri, Man Chan, Isabelle Chai, Rahul Choudhry, Kitae Kim, Stanley Poon, Brian Li, Geeta Deodhar, Elliott Yama
  • Patent number: 10185894
    Abstract: A picture management method and device, a picture synchronization method and device are disclosed. The picture management method can be applied to a client device, and comprises: receiving picture tags generated by a server device performing an image analysis based on original picture features received by the server device, the original picture feature being an original picture itself or original picture parameter(s); and classifying and archiving the original pictures represented by the original picture features according to the picture tags.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: January 22, 2019
    Assignees: BEIJING KUANGSHI TECHNOLOGY CO., LTD., PINHOLE (BEIJING) TECHNOLOGY CO., LTD.
    Inventors: Yuning Jiang, Brian Li
  • Publication number: 20180349324
    Abstract: The present disclosure describes a system, method, and computer program for real-time and computationally efficient calculation of a recommended value range for a quote variable, such as price, discount, volume, or closing time. The system uses the highest-density interval (HDI) of probability density function (PDF) as a recommended or suggested value range for a quote variable. PDFs for the quote variable are precomputed for groups of related inputs, and each PDF is summarized as an array of discrete points. A dimension reduction technique is applied to the PDF inputs in both the training and real-time (non-training) phases to reduce the number of possible combinations of PDFs. During a quote-creation process, a PDF look-up table enables the system to efficiently identify an applicable PDF from the group of precomputed PDFs based on reduced input values.
    Type: Application
    Filed: June 6, 2017
    Publication date: December 6, 2018
    Inventors: Kirk G. Krappé, Neehar Giri, Man Chan, Isabelle Chai, Rahul Choudhry, Kitae Kim, Stanley Poon, Brian Li, Geeta Deodhar, Elliott Yama
  • Publication number: 20160371566
    Abstract: A picture management method and device, a picture synchronization method and device are disclosed. The picture management method can be applied to a client device, and comprises: receiving picture tags generated by a server device performing an image analysis based on original picture features received by the server device, the original picture feature being an original picture itself or original picture parameter(s); and classifying and archiving the original pictures represented by the original picture features according to the picture tags.
    Type: Application
    Filed: March 26, 2015
    Publication date: December 22, 2016
    Inventors: Yuning JIANG, Brian LI
  • Publication number: 20130028442
    Abstract: A loudspeaker that can be bi-wired or not according to a user's preference comprises a case in which is provided a plurality of audio drivers supplied by a respective plurality of audio networks, the networks being supplied (in turn) by a respective plurality of input terminal pairs, further comprising at least one switch bridging the terminals of different pairs, and adapted to selectively connect the terminals to each other.
    Type: Application
    Filed: January 27, 2011
    Publication date: January 31, 2013
    Applicant: GP Acoustics (UK) Limited
    Inventors: Yiu Cheung Brian Li, Steven Halsall
  • Patent number: 8339253
    Abstract: A method for displaying images of a camera associated with a vehicle includes the steps of displaying the images in a first mode if a first condition is satisfied, and displaying the images in a second mode if a second condition is satisfied.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: December 25, 2012
    Assignee: GM Global Technology Operations LLC
    Inventors: William J. Chundrlik, Jr., Brian Li, Kent S. Lybecker
  • Publication number: 20110078574
    Abstract: According to some embodiments, data may be received from a plurality of intelligent electronic devices (e.g., such as a set of protective relays). For each intelligent electronic device, status information may be stored based on the received data. Moreover, the status information may be displayed via a graphical user interface for the plurality of the intelligent electronic devices. The stored status information may also be transmitted to a remote central server via a communication network.
    Type: Application
    Filed: May 4, 2010
    Publication date: March 31, 2011
    Inventors: David W. Bowe, Claudio Cargnelli, Robert Deveaux, Brian Li, Wenhui Luo, Koh Shimizu
  • Publication number: 20110057782
    Abstract: A method for displaying images of a camera associated with a vehicle includes the steps of displaying the images in a first mode if a first condition is satisfied, and displaying the images in a second mode if a second condition is satisfied.
    Type: Application
    Filed: September 8, 2009
    Publication date: March 10, 2011
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS, INC.
    Inventors: WILLIAM J. CHUNDRLIK, JR., BRIAN LI, KENT S. LYBECKER
  • Patent number: 7557042
    Abstract: Floating gates are formed in two separate polysilicon depositions steps resulting in distinct portions. The first formed portions are between isolation regions. A thick insulator is formed over the isolation regions and floating gate portions. The thick insulator is patterned to leave fences over the isolation regions. A thinning process, an isotropic etch in this example, is applied to these fences to make them thinner. Polysilicon sidewall spacers are formed on the sides of these fences. These sidewall spacers become the second portion of the floating gate. These second portions have the desired shape for significantly increasing the capacitance to the subsequently formed control gates, thereby reducing the gate voltage required for programming and erasing made by a relatively robust process.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: July 7, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chi Nan Brian Li, Cheong M. Hong, Rana P. Singh
  • Patent number: 7521317
    Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate comprising silicon, forming a layer of dielectric on the surface of the semiconductor substrate, forming a gate electrode comprising silicon over the layer of dielectric, recessing the layer of dielectric under the gate electrode, filling the recess with a discrete charge storage material, oxidizing a portion of the gate electrode, and oxidizing a portion of the semiconductor substrate.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: April 21, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chi Nan Brian Li, Ko-Min Chang, Cheong M. Hong
  • Patent number: 7227783
    Abstract: A memory and a method for programming a memory device are discussed. The method comprises selecting a cell to program, wherein the cell is coupled to a bit line, applying a first programming pulse, wherein the first programming pulse comprises applying a first voltage to the bit line, verifying if the cell is programmed after applying the first programming pulse, and applying a second programming pulse to the bit line after applying the first programming pulse if the cell is not programmed after applying the first programming pulse, wherein second programming pulse comprises applying a second voltage to the bit line, wherein the second voltage is different than the first voltage.
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: June 5, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Chi Nan Brian Li
  • Patent number: 7115949
    Abstract: In some embodiments, non-volatile memory (NVM) devices are formed on a silicon-on-insulator (SOI) substrate (12) by forming elevated sources and drains (56) in contact with extensions (46) within the top silicon layer (18) of the SOI substrate (12). Buried conductive regions (42) are formed within the top silicon layer (18) below the extensions (46) to mitigate floating body effects that occur when using SOI substrates. In other embodiments, NVM devices are formed using elevated sources and drains (56), extensions (46) and the buried conductive regions (42) in bulk semiconductor substrates. In any embodiment, logic devices may be formed in conjunction with NVM devices, wherein the logic and NVM devices have elevated sources and drains (56), extensions (46) and the buried conductive regions (42).
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: October 3, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Alexander Hoefler, Chi Nan Brian Li, Gowrishankar L. Chindalore
  • Patent number: 7023269
    Abstract: An amplifier including a difference amplifier, said difference amplifier including a first output and a second output which are adapted for providing a PWM signal output to a load by signal difference between said first and said second outputs, said difference amplifier being adapted for operating in at least first and second alternative operating modes which are respectively characterised by first and second operating voltages, wherein during transition from one operating mode to another, the pulse area of the pulses of said first and second outputs of said difference amplifier are changed according to a pre-determined manner so that the pulse area of pulses of said first and second outputs at the end of said transitional mode is equivalent to the pulse area of the pulses of said first and second outputs immediately after the change of operating modes.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: April 4, 2006
    Assignee: GPE International Limited
    Inventors: Yongmin Meng, Longhai Ye, Yiu Cheung Brian Li
  • Patent number: 6911360
    Abstract: An active fuse includes an active fuse geometry (120) that is used to form both a variable resistor (106) and a select transistor (110). In one embodiment, the active fuse geometry is formed in a portion of an active region (160) of a semiconductor substrate (140), and a select gate (124) is disposed over an end portion (123) of the active fuse geometry to form an integral select transistor (110) for use in programming the active fuse. The use of a shared active fuse geometry within the active region allows for reduced area requirements and improved sensing margins.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: June 28, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chi Nan Brian Li, Alexander B. Hoefler, Der-Gao Lin
  • Patent number: 6836435
    Abstract: A method of erasing a semiconductor nonvolatile memory (NVM) so as to compact the distribution of cell erased threshold voltages within a restricted range around a target erased threshold voltage. Erase pulses are applied to NVM cells until a determination is made by, for example, sensing total column source current that adequate erasure has been realized. An optional soft program signal may be applied subsequent to each erase pulse in order to impede over-erasure. Once erasure has been verified, the distribution of erased threshold voltages is compacted by sustaining, for a predetermined length of time, the simultaneous application of a gate voltage that is equal to the target erased threshold voltage and a highly positive drain voltage.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: December 28, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Chi Nan Brian Li
  • Publication number: 20040217439
    Abstract: An active fuse includes an active fuse geometry (120) that is used to form both a variable resistor (106) and a select transistor (110). In one embodiment, the active fuse geometry is formed in a portion of an active region (160) of a semiconductor substrate (140), and a select gate (124) is disposed over an end portion (123) of the active fuse geometry to form an integral select transistor (110) for use in programming the active fuse. The use of a shared active fuse geometry within the active region allows for reduced area requirements and improved sensing margins.
    Type: Application
    Filed: April 29, 2003
    Publication date: November 4, 2004
    Inventors: Chi Nan Brian Li, Alexander B. Hoefler, Der-Gao Lin