Abstract: A method of erasing a semiconductor nonvolatile memory (NVM) so as to compact the distribution of cell erased threshold voltages within a restricted range around a target erased threshold voltage. Erase pulses are applied to NVM cells until a determination is made by, for example, sensing total column source current that adequate erasure has been realized. An optional soft program signal may be applied subsequent to each erase pulse in order to impede over-erasure. Once erasure has been verified, the distribution of erased threshold voltages is compacted by sustaining, for a predetermined length of time, the simultaneous application of a gate voltage that is equal to the target erased threshold voltage and a highly positive drain voltage.

Abstract: A semiconductor device (10) having asymmetric source and drain regions is formed so that either the source or drain region is shorted to an isolated well (22). In one embodiment, the source region includes a source silicide region (42) and a source extension region (28), which are electrically and physically in contact with the well region (22), and the drain region includes a drain silicide region (46), a drain extension region (30) and a deep doped drain region (38). The source and drain regions have a conductivity that is different than that of the isolated well (22) in which they are formed. To prevent the formation of a deep doped source region when the deep doped drain region (38) is formed, a masking layer (34) is patterned to cover the source region during implantation of the deep doped drain region (38).

Abstract: In some embodiments, non-volatile memory (NVM) devices are formed on a silicon-on-insulator (SOI) substrate (12) by forming elevated sources and drains (56) in contact with extensions (46) within the top silicon layer (18) of the SOI substrate (12). Buried conductive regions (42) are formed within the top silicon layer (18) below the extensions (46) to mitigate floating body effects that occur when using SOI substrates. In other embodiments, NVM devices are formed using elevated sources and drains (56), extensions (46) and the buried conductive regions (42) in bulk semiconductor substrates. In any embodiment, logic devices may be formed in conjunction with NVM devices, wherein the logic and NVM devices have elevated sources and drains (56), extensions (46) and the buried conductive regions (42).

Abstract: A first plurality of memory cells (32, 33) connected in series lies within a first well (47) that is separated and electrically isolated (42) from a second plurality of memory cells (36 et al.) connected in series lying within a second well (46). In one embodiment, the first and second wells (46, 47) are doped p-type and are contained within an n-well (48) and a substrate (49). Applying a negative voltage to its corresponding bit line and a positive voltage to its corresponding word line programs a predetermined memory cell within the first plurality. A lesser positive voltage than that applied to the predetermined memory cell's word line is applied to all other bit lines and word lines of non-selected memory cells. By utilizing a negative voltage while programming a memory cell, the magnitude of programming voltages is reduced, thereby, removing the need for an elaborate charge pump to generate a much higher programming voltage.

Abstract: A first plurality of memory cells (32, 33) connected in series lies within a first well (47) that is separated and electrically isolated (42) from a second plurality of memory cells (36 et al.) connected in series lying within a second well (46). In one embodiment, the first and second wells (46, 47) are doped p-type and are contained within an n-well (48) and a substrate (49). Applying a negative voltage to its corresponding bit line and a positive voltage to its corresponding word line programs a predetermined memory cell within the first plurality. A lesser positive voltage than that applied to the predetermined memory cell's word line is applied to all other bit lines and word lines of non-selected memory cells. By utilizing a negative voltage while programming a memory cell, the magnitude of programming voltages is reduced, thereby, removing the need for an elaborate charge pump to generate a much higher programming voltage.

Abstract: Semiconductor devices and processes for forming the same. The semiconductor device includes field isolation regions within trenches lying within a semiconductor device substrate. The trenches include a first trench and a second trench. The device includes a first component region and a second component region. The first component region lies near the first trench, and the second component region lies near the second trench. The semiconductor device includes a feature selected from a group consisting of: (a) a first liner within the first trench, and a second liner within the second trench, wherein the first liner is significantly thicker than the second liner; and (b) the first component region has a first edge with a first radius of curvature near the first trench, and the second component has a second edge with a second radius of curvature near the second trench, wherein the first radius of curvature is significantly greater than the second radius of curvature.