Patents by Inventor Bruce Faure

Bruce Faure has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11867876
    Abstract: An optical article includes a substrate with front and rear main faces, one main face coated with a columnar micro- or nano-structured coating. The substrate and optical article are transparent in at least a part of the visible region ranging from 380 to 780 nm, along at least one incidence angle. The columnar micro- or nano-structured coating includes an array of columns including each a core and an upper layer covering the core, the core and the upper layer being structurally and/or chemically different and have light absorbing properties with an extinction coefficient “k” ?10-2 in the spectrum 250-2500 nm and are able to cause a change in transmission or in reflection of incident light through the optical article as a function of the angle of incidence of light. Also disclosed is a method for manufacturing an optical article including a columnar micro- or nano-structured coating.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: January 9, 2024
    Assignees: Corporation de l'Ecole Polytechnique de Montreal, Essilor International
    Inventors: William Trottier-Lapointe, Bruce Faure, Bill Baloukas, Richard Vernhes, Oleg Zabeida, Ludvik Martinu, Sasha Woodward, Nicolas Desjardins-Lecavalier, Julien Gagnon
  • Publication number: 20210263195
    Abstract: An optical article includes a substrate with front and rear main faces, one main face coated with a columnar micro- or nano-structured coating. The substrate and optical article are transparent in at least a part of the visible region ranging from 380 to 780 nm, along at least one incidence angle. The columnar micro- or nano-structured coating includes an array of columns including each a core and an upper layer covering the core, the core and the upper layer being structurally and/or chemically different and have light absorbing properties with an extinction coefficient “k” ?10-2 in the spectrum 250-2500 nm and are able to cause a change in transmission or in reflection of incident light through the optical article as a function of the angle of incidence of light. Also disclosed is a method for manufacturing an optical article including a columnar micro- or nano-structured coating.
    Type: Application
    Filed: June 13, 2019
    Publication date: August 26, 2021
    Inventors: William TROTTIER-LAPOINTE, Bruce FAURE, Bill BALOUKAS, Richard VERNHES, Oleg ZABEIDA, Ludvik MARTINU, Sasha WOODWARD, Nicolas DESJARDINS-LECAVALIER, Jullen GAGNON
  • Patent number: 10401536
    Abstract: The invention concerns an item comprising a substrate having at least one main surface coated with a layer A in direct contact with a hydrophobic outer layer B, characterized in that said layer A has been obtained by depositing, under ion beam, activated species from at least one compound C, in gas form, containing, in the structure of same: at least one carbon atom, at least one hydrogen atom, at least one Si—X group, in which X is a hydroxy group or a hydrolysable group chosen from the H, halogen, alkoxy, aryloxy and acyloxy groups, —NR1R2 in which R1 and R2 separately designate a hydrogen atom, an alkyl group or an aryl group, and —N(R3)—Si in which R3 designates an alkyl group or an aryl group, said compound C being neither tetramethyldisiloxane nor tetraethoxysilane, nor vinylmethyldiethoxysilane, nor hexamethylcyclotrisilazane, said layer A not being formed from inorganic precursor compounds.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: September 3, 2019
    Assignee: Essilor International
    Inventors: Sebastien Chiarotto, Bruce Faure, Stephanie Pega, Karin Scherer
  • Publication number: 20160139304
    Abstract: The invention concerns an item comprising a substrate having at least one main surface coated with a layer A in direct contact with a hydrophobic outer layer B, characterised in that said layer A has been obtained by depositing, under ion beam, activated species from at least one compound C, in gas form, containing, in the structure of same: at least one carbon atom, at least one hydrogen atom, at least one Si—X group, in which X is a hydroxy group or a hydrolysable group chosen from the H, halogen, alkoxy, aryloxy and acyloxy groups, —NR1R2 in which R1 and R2 separately designate a hydrogen atom, an alkyl group or an aryl group, and —N(R3)—Si in which R3 designates an alkyl group or an aryl group, said compound C being neither tetramethyldisiloxane nor tetraethoxysilane, nor vinylmethyldiethoxysilane, nor hexamethylcyclotrisilazane, said layer A not being formed from inorganic precursor compounds.
    Type: Application
    Filed: June 13, 2014
    Publication date: May 19, 2016
    Applicant: ESSILOR INTERNATIONAL (COMPAGNIE GENERALE D'OPTIQUE)
    Inventors: Sebastien Chiarotto, Bruce Faure, Stephanie Pega, Karin Scherer
  • Patent number: 9242444
    Abstract: A method of preventing microcavity formation in a bonding layer of a composite structure resulting from creep and thermal expansion due to high temperature exposure of the composite structure. The method includes the steps of providing a thin film with a thickness of 5 micrometers or less; providing a bonding layer of oxide with a thickness that is equal to or greater than the thickness of the thin film with the bonding layer formed by low pressure chemical vapor deposition. The thin film or support substrate have a mean thermal expansion coefficient of 7×10?6 K?1 or more. The thin film, bonding layer and support substrate combine to reduce stress in and plastic deformation of the bonding layer during exposure to high temperatures of more than approximately 900° C. to thus prevent microcavities from appearing in the bonding layer.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: January 26, 2016
    Assignee: SOITEC
    Inventors: Bruce Faure, Alexandra Marcovecchio
  • Patent number: 9041165
    Abstract: A method for the formation of an at least partially relaxed strained material layer, comprises providing a seed substrate; patterning the seed substrate; growing a strained material layer on the patterned seed substrate; transferring the strained material layer from the patterned seed substrate to an intermediate substrate; and at least partially relaxing the strained material layer by a heat treatment.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: May 26, 2015
    Assignee: SOITEC
    Inventors: Fabrice Letertre, Bruce Faure, Pascal Guenard
  • Patent number: 9011598
    Abstract: The present invention provides methods for fabricating a composite substrate including a supporting substrate and a layer of a binary or ternary material having a crystal form that is non-cubic and semi-polar or non-polar. The methods comprise transferring the layer of a binary or ternary material from a donor substrate to a receiving substrate.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: April 21, 2015
    Assignee: Soitec
    Inventors: Alice Boussagol, Frédéric Dupont, Bruce Faure
  • Patent number: 8912081
    Abstract: The present invention relates to a method for relaxing a strained material layer by providing a strained material layer and a low-viscosity layer formed on a first face of the strained material layer; forming a stiffening layer on at least one part of a second face of the strained material layer opposite to the first face thereby forming a multilayer stack; and subjecting the multilayer stack to a heat treatment thereby at least partially relaxing the strained material layer.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: December 16, 2014
    Assignee: SOITEC
    Inventor: Bruce Faure
  • Publication number: 20140014029
    Abstract: A method of preventing microcavity formation in the bonding layer of a composite structure resulting from creep and thermal expansion due to high temperature exposure of the composite structure The method includes the steps of providing the thin film with a thickness of 5 micrometers or less; providing the bonding layer of oxide with a thickness that is equal to or greater than the thickness of the thin film with the bonding layer formed by low pressure chemical vapor deposition. The thin film or support substrate have a mean thermal expansion coefficient of 7×10?6 K?1 or more. The thin film, bonding layer and support substrate combine to reduce stress in and plastic deformation of the bonding layer during exposure to during exposure to high temperatures of more than approximately 900° C. to thus prevent microcavities from appearing in the bonding layer.
    Type: Application
    Filed: September 19, 2013
    Publication date: January 16, 2014
    Applicant: SOITEC
    Inventors: Bruce FAURE, Alexandra MARCOVECCHIO
  • Patent number: 8564019
    Abstract: The invention relates to a process for fabricating a heterostructure. This process is noteworthy in that it comprises the following steps: a) a strained crystalline thin film is deposited on, or transferred onto, an intermediate substrate; b) a strain relaxation layer, made of crystalline material capable of being plastically deformed by a heat treatment at a relaxation temperature at which the material constituting the thin film deforms by elastic deformation is deposited on the thin film; c) the thin film and the relaxation layer are transferred onto a substrate; and d) a thermal budget is applied at at least the relaxation temperature, so as to cause the plastic deformation of the relaxation layer and the at least partial relaxation of the thin film by elastic deformation, and thus to obtain the final heterostructure.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: October 22, 2013
    Assignee: Soitec
    Inventor: Bruce Faure
  • Patent number: 8541290
    Abstract: A method of fabricating a device by providing an auxiliary substrate having a metal nitride layer disposed thereon where the nitride layer has a nitrogen face and an opposite face and a dislocation density that is less than about 106, with the nitrogen face of the nitride layer facing the auxiliary substrate; depositing at least one epitaxial nitride layer on the exposed opposite face of the nitride layer of the structure; depositing a further metal layer over at least a portion of the epitaxial nitride layer(s); bonding a final substrate on the deposited metal layer; and removing the auxiliary substrate to form the device from the final substrate and deposited layers. Preferably, the device that is formed includes a LED or laser.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: September 24, 2013
    Assignee: Soitec
    Inventors: Fabrice Letertre, Bruce Faure
  • Patent number: 8492244
    Abstract: The present invention provides methods for forming at least partially relaxed strained material layers on a target substrate. The methods include forming islands of the strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment, and transferring the at least partially relaxed strained material islands to the target substrate. The at least partial relaxation is facilitated by the presence of low-viscosity or compliant layers adjacent to the strained material layer. The invention also provides semiconductor structures having an at least partially relaxed strained material layer, and semiconductor devices fabricated using an at least partially relaxed strained material layer.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: July 23, 2013
    Assignee: Soitec
    Inventors: Pascal Guenard, Bruce Faure, Fabrice Letertre, Michael R. Krames, Nathan F. Gardner, Melvin B. McLaurin
  • Patent number: 8486771
    Abstract: Methods of fabricating relaxed layers of semiconductor materials include forming structures of a semiconductor material overlying a layer of a compliant material, and subsequently altering a viscosity of the compliant material to reduce strain within the semiconductor material. The compliant material may be reflowed during deposition of a second layer of semiconductor material. The compliant material may be selected so that, as the second layer of semiconductor material is deposited, a viscosity of the compliant material is altered imparting relaxation of the structures. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Methods of fabricating semiconductor structures and devices are also disclosed. Novel intermediate structures are formed during such methods.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: July 16, 2013
    Assignee: Soitec
    Inventors: Fabrice Letertre, Bruce Faure, Michael R. Krames, Nathan F. Gardner
  • Patent number: 8481407
    Abstract: The invention relates to a process for fabricating a heterostructure. This process comprises heating an intermediate heterostructure. The intermediate heterostructure comprises a crystalline strain relaxation layer interposed directly between a first substrate and a strained layer of crystalline semiconductor material. The process further comprises causing plastic deformation of the crystalline strain relaxation layer and elastic deformation of the strained layer of crystalline semiconductor material to at least partially relax the strained layer of crystalline semiconductor material.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: July 9, 2013
    Assignee: Soitec
    Inventor: Bruce Faure
  • Patent number: 8263984
    Abstract: In some embodiments, the invention relates to a process for making a GaN substrate comprising: transferring a first monocrystal GaN layer onto a supporting substrate; applying crystal growth for a second monocrystal GaN layer on the first layer; the first and second GaN layers thereby forming together the GaN substrate, the GaN substrate having a thickness of at least 10 micrometers, and removing at least one portion of the supporting substrate.
    Type: Grant
    Filed: November 11, 2007
    Date of Patent: September 11, 2012
    Assignee: Soitec
    Inventor: Bruce Faure
  • Patent number: 8216368
    Abstract: A method of forming an epitaxially grown layer, preferably by providing a region of weakness in a support substrate and transferring a nucleation portion to the support substrate by bonding. A remainder portion of the support substrate is detached at the region of weakness and an epitaxial layer is grown on the nucleation portion. The remainder portion is separated or otherwise removed from the support portion.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: July 10, 2012
    Assignee: Soitec
    Inventors: Bruce Faure, Fabrice Letertre
  • Publication number: 20120100691
    Abstract: The invention relates to a process for fabricating a heterostructure. This process comprises heating an intermediate heterostructure. The intermediate heterostructure comprises a crystalline strain relaxation layer interposed directly between a first substrate and a strained layer of crystalline semiconductor material. The process further comprises causing plastic deformation of the crystalline strain relaxation layer and elastic deformation of the strained layer of crystalline semiconductor material to at least partially relax the strained layer of crystalline semiconductor material.
    Type: Application
    Filed: December 30, 2011
    Publication date: April 26, 2012
    Applicant: Soitec
    Inventor: Bruce Faure
  • Publication number: 20120098033
    Abstract: The invention relates to a process for fabricating a heterostructure. This process is noteworthy in that it comprises the following steps: a) a strained crystalline thin film is deposited on, or transferred onto, an intermediate substrate; b) a strain relaxation layer, made of crystalline material capable of being plastically deformed by a heat treatment at a relaxation temperature at which the material constituting the thin film deforms by elastic deformation is deposited on the thin film; c) the thin film and the relaxation layer are transferred onto a substrate; and d) a thermal budget is applied at at least the relaxation temperature, so as to cause the plastic deformation of the relaxation layer and the at least partial relaxation of the thin film by elastic deformation, and thus to obtain the final heterostructure.
    Type: Application
    Filed: December 30, 2011
    Publication date: April 26, 2012
    Applicant: SOITEC
    Inventor: Bruce Faure
  • Patent number: 8153500
    Abstract: A method of fabricating materials by epitaxy by epitaxially growing at least one layer of a material upon a composite structure that has at least one thin film bonded to a support substrate and a bonding layer of oxide formed by deposition between the support substrate and the thin film. The thin film and the support substrate have a mean thermal expansion coefficient of 7×10?6 K?1 or more. The bonding layer is formed by low pressure chemical vapor deposition (LPCVD) of a layer of silicon oxide on the bonding face of the support substrate or on the bonding face of the thin film. The thin film has a thickness of 5 micrometers or less while the thickness of the layer of oxide is equal to or greater than the thickness of the thin film. The method also includes a heat treatment carried out at a temperature that is higher than the temperature for deposition of the layer of oxide of silicon and for a predetermined period.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: April 10, 2012
    Assignee: Soitec
    Inventors: Bruce Faure, Alexandra Marcovecchio
  • Patent number: 8105916
    Abstract: The invention relates to a process for fabricating a heterostructure. This process is noteworthy in that it comprises the following steps: a) a strained crystalline thin film is deposited on, or transferred onto, an intermediate substrate; b) a strain relaxation layer, made of crystalline material capable of being plastically deformed by a heat treatment at a relaxation temperature at which the material constituting the thin film deforms by elastic deformation is deposited on the thin film; c) the thin film and the relaxation layer are transferred onto a substrate; and d) a thermal budget is applied at least the relaxation temperature, so as to cause the plastic deformation of the relaxation layer and the at least partial relaxation of the thin film by elastic deformation, and thus to obtain the final heterostructure.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: January 31, 2012
    Assignee: S.O.I. Tec Silicon on Insulator Technologies
    Inventor: Bruce Faure