Patents by Inventor Bruce Faure

Bruce Faure has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8093138
    Abstract: A method of forming an epitaxially grown layer by forming a region of weakness in a support substrate to define a support portion and a remainder portion on opposite sides of the region of weakness, epitaxially growing an epitaxially grown layer on the support portion after forming the region of weakness but prior to detachment of the support portion from the remainder portion; bonding the epitaxially grown layer to an acceptor substrate before detaching the remainder portion from the support portion; and detaching the remainder portion from the support portion at the region of weakness. The epitaxially grown layer may be removed from the support portion as a free-standing structure.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: January 10, 2012
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruce Faure, Lea Di Cioccio
  • Publication number: 20110291247
    Abstract: The present invention relates to a method for the formation of an at least partially relaxed strained material layer, the method comprising the steps of providing a seed substrate; patterning the seed substrate; growing a strained material layer on the patterned seed substrate; transferring the strained material layer from the patterned seed substrate to an intermediate substrate; and at least partially relaxing the strained material layer by a heat treatment.
    Type: Application
    Filed: January 11, 2010
    Publication date: December 1, 2011
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Fabrice Letertre, Bruce Faure, Pascal Guenard
  • Publication number: 20110237008
    Abstract: A method of fabricating a device by providing an auxiliary substrate having a metal nitride layer disposed thereon where the nitride layer has a nitrogen face and an opposite face and a dislocation density that is less than about 106, with the nitrogen face of the nitride layer facing the auxiliary substrate; depositing at least one epitaxial nitride layer on the exposed opposite face of the nitride layer of the structure; depositing a further metal layer over at least a portion of the epitaxial nitride layer(s); bonding a final substrate on the deposited metal layer; and removing the auxiliary substrate to form the device from the final substrate and deposited layers. Preferably, the device that is formed includes a LED or laser.
    Type: Application
    Filed: June 7, 2011
    Publication date: September 29, 2011
    Inventors: Fabrice Letertre, Bruce Faure
  • Publication number: 20110180911
    Abstract: The present invention provides methods for forming at least partially relaxed strained material layers on a target substrate. The methods include forming islands of the strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment, and transferring the at least partially relaxed strained material islands to the target substrate. The at least partial relaxation is facilitated by the presence of low-viscosity or compliant layers adjacent to the strained material layer. The invention also provides semiconductor structures having an at least partially relaxed strained material layer, and semiconductor devices fabricated using an at least partially relaxed strained material layer.
    Type: Application
    Filed: April 7, 2011
    Publication date: July 28, 2011
    Inventors: Pascal Guenard, Bruce Faure, Fabrice Letertre, Michael R. Krames, Nathan F. Gardner, Melvin B. McLaurin
  • Patent number: 7981767
    Abstract: The present invention provides methods for forming at least partially relaxed strained material layers on a target substrate. The methods include forming islands of the strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment, and transferring the at least partially relaxed strained material islands to the target substrate. The at least partial relaxation is facilitated by the presence of low-viscosity or compliant layers adjacent to the strained material layer. The invention also provides semiconductor structures having an at least partially relaxed strained material layer, and semiconductor devices fabricated using an at least partially relaxed strained material layer.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: July 19, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Pascal Guenard, Bruce Faure, Fabrice Letertre, Michael R. Krames, Nathan F. Gardner, Melvin B. McLaurin
  • Publication number: 20110127640
    Abstract: The present invention relates to a method for relaxing a strained material layer by providing a strained material layer and a low-viscosity layer formed on a first face of the strained material layer; forming a stiffening layer on at least one part of a second face of the strained material layer opposite to the first face thereby forming a multilayer stack; and subjecting the multilayer stack to a heat treatment thereby at least partially relaxing the strained material layer.
    Type: Application
    Filed: July 2, 2009
    Publication date: June 2, 2011
    Inventor: Bruce Faure
  • Patent number: 7939428
    Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving substrate and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: May 10, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative
  • Publication number: 20110039368
    Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving substrate and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.
    Type: Application
    Filed: October 28, 2010
    Publication date: February 17, 2011
    Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, Gisèle Rayssac
  • Patent number: 7839001
    Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: November 23, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, legal representative, Giséle Rayssac, legal representative
  • Publication number: 20100190000
    Abstract: A method of fabricating a composite structure that has at least one thin film bonded to a support substrate and a bonding layer of oxide formed by deposition between the support substrate and the thin film. The thin film and the support substrate have a mean thermal expansion coefficient of 7×10?6 K?1 or more. The bonding layer of oxide is formed by low pressure chemical vapor deposition (LPCVD) of a layer of oxide on the bonding face of the support substrate or on the bonding face of the thin film. The thin film has a thickness of 5 micrometers or less while the thickness of the layer of oxide is equal to or greater than the thickness of the thin film.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 29, 2010
    Applicant: S.O.I.Tec silicon on Insulator Technologies
    Inventors: Bruce Faure, Alexandra Marcovecchio
  • Publication number: 20100178749
    Abstract: A method of fabricating materials by epitaxy by epitaxially growing at least one layer of a material upon a composite structure that has at least one thin film bonded to a support substrate and a bonding layer of oxide formed by deposition between the support substrate and the thin film. The thin film and the support substrate have a mean thermal expansion coefficient of 7×10?6 K?1 or more. The bonding layer is formed by low pressure chemical vapor deposition (LPCVD) of a layer of silicon oxide on the bonding face of the support substrate or on the bonding face of the thin film. The thin film has a thickness of 5 micrometers or less while the thickness of the layer of oxide is equal to or greater than the thickness of the thin film. The method also includes a heat treatment carried out at a temperature that is higher than the temperature for deposition of the layer of oxide of silicon and for a predetermined period.
    Type: Application
    Filed: January 6, 2009
    Publication date: July 15, 2010
    Applicant: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruce Faure, Alexandra Marcovecchio
  • Publication number: 20100176490
    Abstract: Methods of fabricating relaxed layers of semiconductor materials include forming structures of a semiconductor material overlying a layer of a compliant material, and subsequently altering a viscosity of the compliant material to reduce strain within the semiconductor material. The compliant material may be reflowed during deposition of a second layer of semiconductor material. The compliant material may be selected so that, as the second layer of semiconductor material is deposited, a viscosity of the compliant material is altered imparting relaxation of the structures. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Methods of fabricating semiconductor structures and devices are also disclosed. Novel intermediate structures are formed during such methods.
    Type: Application
    Filed: September 21, 2009
    Publication date: July 15, 2010
    Inventors: Fabrice LETERTRE, Bruce FAURE, Michael R. Krames, Nathan F. GARDNER
  • Patent number: 7736935
    Abstract: The present invention provides, in part, methods producing multilayer semiconductor structures having one or more at least partially relaxed strained layers, where the strained layer is at least partially relaxed by annealing. In particular, the invention forms diffusion barriers that prevent diffusion of contaminants during annealing. The invention also includes embodiments where the at least partially relaxed strained layer is patterned into islands by etching trenches and the like. The invention also provides semiconductor structures resulting from these methods, and further, provides such structures where the semiconductor materials are suitable for application to LED devices, laser devices, photovoltaic devices, and other optoelectronic devices.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: June 15, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruce Faure, Pascal Guenard
  • Patent number: 7670930
    Abstract: A method of fabricating a thin film from a substrate includes implantation into the substrate, for example made of silicon, of ions of a non-gaseous species, for example gallium, the implantation conditions and this species being chosen, according to the material of the substrate, so as to allow the formation of precipitates confined in a certain depth, distributed within a layer, these precipitates being made of a solid phase having a melting point below that of the substrate. The method optionally further including intimate contacting of this face of the substrate with a stiffener, and detachment of a thin film by fracturing the substrate at the layer of precipitates by applying a mechanical and/or chemical detachment stress under conditions in which the precipitates are in the liquid phase.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: March 2, 2010
    Assignees: Commissariat a l 'Energie Atomique, S.O.I. Tec-Silicon on Insulator Technologies
    Inventors: Aurélie Tauzin, Bruce Faure, Arnaud Garnier
  • Publication number: 20100035418
    Abstract: The present invention provides, in part, methods producing multilayer semiconductor structures having one or more at least partially relaxed strained layers, where the strained layer is at least partially relaxed by annealing. In particular, the invention forms diffusion barriers that prevent diffusion of contaminants during annealing. The invention also includes embodiments where the at least partially relaxed strained layer is patterned into islands by etching trenches and the like. The invention also provides semiconductor structures resulting from these methods, and further, provides such structures where the semiconductor materials are suitable for application to LED devices, laser devices, photovoltaic devices, and other optoelectronic devices.
    Type: Application
    Filed: December 22, 2008
    Publication date: February 11, 2010
    Inventors: Bruce FAURE, Pascal Guenard
  • Publication number: 20100032793
    Abstract: The present invention provides methods for forming at least partially relaxed strained material layers on a target substrate. The methods include forming islands of the strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment, and transferring the at least partially relaxed strained material islands to the target substrate. The at least partial relaxation is facilitated by the presence of low-viscosity or compliant layers adjacent to the strained material layer. The invention also provides semiconductor structures having an at least partially relaxed strained material layer, and semiconductor devices fabricated using an at least partially relaxed strained material layer.
    Type: Application
    Filed: December 22, 2008
    Publication date: February 11, 2010
    Inventors: Pascal Guenard, Bruce Faure, Fabrice Letertre, Michael R. Krames, Nathan F. Gardner, Melvin B. McLaurin
  • Publication number: 20100025728
    Abstract: The invention relates to a process for fabricating a heterostructure. This process is noteworthy in that it comprises the following steps: a) a strained crystalline thin film is deposited on, or transferred onto, an intermediate substrate; b) a strain relaxation layer, made of crystalline material capable of being plastically deformed by a heat treatment at a relaxation temperature, at which the material constituting the thin film deforms by elastic deformation is deposited on the thin film; c) the thin film and the relaxation layer are transferred onto a substrate; and d) a thermal budget is applied at at least the relaxation temperature, so as to cause the plastic deformation of the relaxation layer and the at least partial relaxation of the thin film by elastic deformation, and thus to obtain the final heterostructure.
    Type: Application
    Filed: May 11, 2009
    Publication date: February 4, 2010
    Inventor: Bruce Faure
  • Publication number: 20100012947
    Abstract: The invention relates to a process for making a GaN substrate (60), characterized in that it comprises the following steps: (a) transferring a first monocrystal GaN layer (50) onto a supporting substrate (40); (b) applying crystal growth for a second monocrystal GaN layer on the first layer (50); the first and second GaN layers thereby forming together said GaN substrate (60), said GaN substrate (60) having a thickness of at least 10 micrometers, (c) removing at least one portion of the supporting substrate (40).
    Type: Application
    Filed: November 11, 2007
    Publication date: January 21, 2010
    Inventor: Bruce Faure
  • Patent number: 7646038
    Abstract: An efficient method of fabricating a high-quality heteroepitaxial microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a heteroepitaxial microstructure on the detached surface of the carrier substrate by depositing an epitaxial layer on the detached surface of a carrier substrate. Also included is a heteroepitaxial microstructure fabricated from such method.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: January 12, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruce Faure, Fabrice Letertre, Bruno Ghyselen
  • Publication number: 20090321884
    Abstract: A method of forming an epitaxially grown layer, preferably by providing a region of weakness in a support substrate and transferring a nucleation portion to the support substrate by bonding. A remainder portion of the support substrate is detached at the region of weakness and an epitaxial layer is grown on the nucleation portion. The remainder portion is separated or otherwise removed from the support portion.
    Type: Application
    Filed: September 3, 2009
    Publication date: December 31, 2009
    Inventors: Bruce Faure, Fabrice Letertre