Patents by Inventor Bruce Faure
Bruce Faure has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20090325362Abstract: A method for forming a semiconductor structure that includes a thin layer of semiconductor material on a receiver wafer is disclosed. The method includes removing a thickness of material from a donor wafer, which comprises a support substrate and an epitaxial layer, for surface preparation and transferring a portion of the epitaxial layer from the donor wafer to the receiver wafer. The thickness removed during the surface preparation is adapted to enable formation of a new semiconductor structure from the remaining epitaxial portion of the donor wafer.Type: ApplicationFiled: July 15, 2009Publication date: December 31, 2009Inventors: Nabil Chhaimi, Eric Guiot, Patrick Reynaud, Bruno Ghyselen, Cécile Aulnette, Bénédicte Osternaud, Takeshi Akatsu, Bruce Faure
-
Publication number: 20090289332Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.Type: ApplicationFiled: August 5, 2009Publication date: November 26, 2009Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, Gisele Rayssac
-
Patent number: 7615468Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.Type: GrantFiled: August 17, 2007Date of Patent: November 10, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative
-
Patent number: 7601217Abstract: A method of forming an epitaxially grown layer, preferably by providing a region of weakness in a support substrate and transferring a nucleation portion to the support substrate by bonding. A remainder portion of the support substrate is detached at the region of weakness and an epitaxial layer is grown on the nucleation portion. The remainder portion is separated or otherwise removed from the support portion.Type: GrantFiled: November 22, 2005Date of Patent: October 13, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Bruce Faure, Fabrice Letertre
-
Patent number: 7602046Abstract: The invention relates to a recyclable donor wafer that includes a substrate and a formed layer thereon, wherein the formed layer has a thickness sufficient to provide (a) at least two useful layers for detachment therefrom and (b) additional material that can be removed to planarize exposed surfaces of the useful layers prior to detachment from the donor wafer.Type: GrantFiled: March 7, 2005Date of Patent: October 13, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Bruno Ghyselen, Cécile Aulnette, Bénédite Osternaud, Takeshi Akatsu, Bruce Faure
-
Publication number: 20090229743Abstract: A method of forming an epitaxially grown layer by forming a region of weakness in a support substrate to define a support portion and a remainder portion on opposite sides of the region of weakness, epitaxially growing an epitaxially grown layer on the support portion after forming the region of weakness but prior to detachment of the support portion from the remainder portion; bonding the epitaxially grown layer to an acceptor substrate before detaching the remainder portion from the support portion; and detaching the remainder portion from the support portion at the region of weakness. The epitaxially grown layer may be removed from the support portion as a free-standing structure.Type: ApplicationFiled: May 20, 2009Publication date: September 17, 2009Applicant: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Bruce Faure, Lea Di Cioccio
-
Publication number: 20090200569Abstract: A method of producing an optoelectronic substrate by detaching a thin layer from a semi-conducting nitride substrate and transferring it to an auxiliary substrate to provide at least one semi-conducting nitride layer thereon, metallizing at least a portion of the surface of the auxiliary substrate that includes the transferred nitride layer, bonding to a final substrate the metallized surface portion of the transferred nitrate layer of the auxiliary substrate, and removing the auxiliary substrate to provide an optoelectronic substrate comprising a semi-conducting nitride surface layer over a subjacent metallized portion and a supporting final substrate. Resultant optoelectronic substrates having low dislocation densities are also included.Type: ApplicationFiled: April 16, 2009Publication date: August 13, 2009Inventors: Fabrice Letertre, Bruce Faure
-
Patent number: 7538010Abstract: A method of forming an epitaxially grown layer by providing a support substrate that includes a region of weakness therein to define a support portion and a remainder portion on opposite sides of the region of weakness. The region of weakness comprises atomic species implanted in the support substrate to facilitate detachment of the support portion from the remainder portion. The method also includes epitaxially growing an epitaxially grown layer in association with the support portion.Type: GrantFiled: November 22, 2005Date of Patent: May 26, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Bruce Faure, Lea Di Cioccio
-
Patent number: 7537949Abstract: A method of producing an optoelectronic substrate by detaching a thin layer from a semi-conducting nitride substrate and transferring it to an auxiliary substrate to provide at least one semi-conducting nitride layer thereon, metallizing at least a portion of the surface of the auxiliary substrate that includes the transferred nitride layer, bonding to a final substrate the metallized surface portion of the transferred nitrate layer of the auxiliary substrate, and removing the auxiliary substrate to provide an optoelectronic substrate comprising a semi-conducting nitride surface layer over a subjacent metallized portion and a supporting final substrate. Resultant optoelectronic substrates having low dislocation densities are also included.Type: GrantFiled: March 21, 2005Date of Patent: May 26, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Fabrice Letertre, Bruce Faure
-
Publication number: 20090061594Abstract: A method of fabricating a thin film from a substrate includes implantation into the substrate, for example made of silicon, of ions of a non-gaseous species, for example gallium, the implantation conditions and this species being chosen, according to the material of the substrate, so as to allow the formation of precipitates confined in a certain depth, distributed within a layer, these precipitates being made of a solid phase having a melting point below that of the substrate. The method optionally further including intimate contacting of this face of the substrate with a stiffener, and detachment of a thin film by fracturing the substrate at the layer of precipitates by applying a mechanical and/or chemical detachment stress under conditions in which the precipitates are in the liquid phase.Type: ApplicationFiled: March 28, 2007Publication date: March 5, 2009Inventors: Aurelie Tauzin, Bruce Faure, Arnaud Garnier
-
Publication number: 20080210975Abstract: An efficient method of fabricating a high-quality heteroepitaxial microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a heteroepitaxial microstructure on the detached surface of the carrier substrate by depositing an epitaxial layer on the detached surface of a carrier substrate. Also included is a heteroepitaxial microstructure fabricated from such method.Type: ApplicationFiled: September 10, 2007Publication date: September 4, 2008Applicant: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Bruce Faure, Fabrice Letertre, Bruno Ghyselen
-
Patent number: 7375008Abstract: The invention relates to a method of re-forming a useful layer on a donor wafer after taking off a useful layer formed of a material chosen from among semiconductor materials. The donor wafer includes in succession a substrate and a taking-off structure, the taking-off structure includes the taken-off useful layer before taking-off. The method includes a removal of material involving a portion of the donor wafer on the side where the useful layer has been taken off. The material is removed by mechanical means so as to preserve a portion of the taking-off structure to form at least one other useful layer which can be taken off after re-forming, without adding additional material to the wafer.Type: GrantFiled: March 7, 2005Date of Patent: May 20, 2008Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Bruno Ghyselen, Cécile Aulnette, Bénédite Osternaud, Takeshi Akatsu, Bruce Faure
-
Publication number: 20070287273Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.Type: ApplicationFiled: August 17, 2007Publication date: December 13, 2007Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, Gisele Rayssac
-
Patent number: 7288430Abstract: An efficient method of fabricating a high-quality heteroepitaxial microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a heteroepitaxial microstructure on the detached surface of the carrier substrate by depositing an epitaxial layer on the detached surface of a carrier substrate. Also included is a heteroepitaxial microstructure fabricated from such method.Type: GrantFiled: June 24, 2005Date of Patent: October 30, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnolgoiesInventors: Bruce Faure, Fabrice Letertre, Bruno Ghyselen
-
Patent number: 7261777Abstract: A method for fabricating an epitaxial substrate. The technique includes providing a crystalline or mono-crystalline base substrate, implanting atomic species into a front face of the base substrate to a controlled mean implantation depth to form a zone of weakness within the base substrate that defines a sub-layer, and growing a stiffening layer on a front face of the base substrate by using a thermal treatment in a first temperature range. The stiffening layer has a thickness sufficient to form an epitaxial substrate. In addition, the method includes detaching the stiffening layer and the sub-layer from the base substrate by using a thermal treatment in a second temperature range higher than the first temperature range. An epitaxial substrate and a remainder of the base substrate are obtained. The epitaxial substrate is suitable for use in growing high quality homoepitaxial or heteroepitaxial films thereon.Type: GrantFiled: June 1, 2004Date of Patent: August 28, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventor: Bruce Faure
-
Patent number: 7256473Abstract: A composite structure is disclosed that includes a support wafer and a layered structure on the support wafer. The layered structure includes at least one layer of a monocrystalline material and at least one layer of a dielectric material. In addition, the layered structure materials and the thickness of each layer are chosen such that the thermal impedance between ambient temperature and 600° K of the composite structure is a value that is no greater than about 1.3 times the thermal impedance of a monocrystalline bulk SiC wafer having the same dimensions as the composite structure. The composite structure provides sufficient heat dissipation properties for manufacturing optical, electronic, or optoelectronic components.Type: GrantFiled: October 6, 2006Date of Patent: August 14, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Bruce Faure, Alice Boussagol
-
Publication number: 20070141803Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support.Type: ApplicationFiled: August 16, 2006Publication date: June 21, 2007Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen
-
Patent number: 7229898Abstract: Improved fabrication processes for manufacturing GeOI type wafers are disclosed. In an implementation, a method for fabricating a germanium on insulator wafer includes providing a source substrate having a surface, at least a layer of germanium and a weakened area. The weakened area is located at a predetermined depth in the germanium layer of the source substrate and is generally parallel to the source substrate surface. The technique also includes providing a germanium oxynitride layer in or on the source substrate, bonding the source substrate surface to a handle substrate to form a source-handle structure, and detaching the source substrate from the source-handle structure at the weakened area of the source substrate to create the germanium on insulator wafer having, as a surface, a useful layer of germanium.Type: GrantFiled: January 4, 2005Date of Patent: June 12, 2007Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Konstantin Bourdelle, Fabrice Letertre, Bruce Faure, Christophe Morales, Chrystel Deguet
-
Patent number: 7226509Abstract: A method for fabricating a carrier substrate. The technique includes providing a crystalline or mono-crystalline base substrate, growing a stiffening layer on a front face of the base substrate at a thickness sufficient to form a carrier substrate for subsequent processing, and detaching the stiffening layer from the base substrate to obtain the carrier substrate and a remainder of the base substrate. The carrier substrate is suitable for use in growing high quality homo-epitaxial or hetero-epitaxial films thereon.Type: GrantFiled: November 18, 2003Date of Patent: June 5, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventor: Bruce Faure
-
Publication number: 20070080372Abstract: A composite structure is disclosed that includes a support wafer and a layered structure on the support wafer. The layered structure includes at least one layer of a monocrystalline material and at least one layer of a dielectric material. In addition, the layered structure materials and the thickness of each layer are chosen such that the thermal impedance between ambient temperature and 600° K of the composite structure is a value that is no greater than about 1.3 times the thermal impedance of a monocrystalline bulk SiC wafer having the same dimensions as the composite structure. The composite structure provides sufficient heat dissipation properties for manufacturing optical, electronic, or optoelectronic components.Type: ApplicationFiled: October 6, 2006Publication date: April 12, 2007Inventors: Bruce Faure, Boussagol Alice