Abstract: A memory architecture for 3-dimensional thyristor cell arrays is disclosed. Thyristor memory cells are connected in a 3-dimensional cross-point array to form a bit line cluster. The bit line clusters are connected in parallel to sense amplifier and write circuits through multiplexer/demultiplexer circuits. Control circuits select one of the bit line clusters during a read or write operation while the non-selected bit line clusters are not activated to avoid disturbs and power consumption in the non-selected bit line clusters. The bit line clusters, multiplexer/demultiplexer circuits, and sense amplifier and write circuits from a memory array tile (MAT).

Abstract: A memory architecture for 3-dimensional thyristor cell arrays is disclosed. Thyristor memory cells are connected in a 3-dimensional cross-point array to form a bit line cluster. The bit line clusters are connected in parallel to sense amplifier and write circuits through multiplexer/demultiplexer circuits. Control circuits select one of the bit line clusters during a read or write operation while the non-selected bit line clusters are not activated to avoid disturbs and power consumption in the non-selected bit line clusters. The bit line clusters, multiplexer/demultiplexer circuits, and sense amplifier and write circuits from a memory array tile (MAT).

Abstract: A memory architecture for 3-dimensional thyristor cell arrays is disclosed. Thyristor memory cells are connected in a 3-dimensional cross-point array to form a bit line cluster. The bit line clusters are connected in parallel to sense amplifier and write circuits through multiplexer/demultiplexer circuits. Control circuits select one of the bit line clusters during a read or write operation while the non-selected bit line clusters are not activated to avoid disturbs and power consumption in the non-selected bit line clusters. The bit line clusters, multiplexer/demultiplexer circuits, and sense amplifier and write circuits from a memory array tile (MAT).

Abstract: A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

Abstract: A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

Abstract: A memory device may include a local bit line electrically coupled to a plurality of memory cells and a global bit line electrically coupled to the local bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path may be active and the second path may be in an off state in at least one of a set operation or a forming operation. The second path may be active in a reset operation, wherein the second impedance of the second path has a lower impedance than the first impedance of the first path.

Abstract: A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

Abstract: Aspects of DDR and thyristor memory cell RAMs are optimally combined for high-speed data transfer into and out of RAMs. After a Read operation in which data from a selected row of memory cells in an array are latched, a Burst operation selectively moves the latched data from the array or latches external data. At the same time as the Burst data transfer, all the memory cells of the selected row are turned off or on by a write operation. In the following Write-Back & Pre-charge operation, the latched data bits which are complementary to the memory cell state of the Burst write operation are written back into the corresponding memory cells in the selected row. As part of a DDR-like activation cycle, data can be transferred to and from the memory cell array RAM at high-speed.

Abstract: Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled with various techniques including encoding the data stored in the arrays.

Abstract: Operations with reduced current overall are performed on single thyristor memory cells forming a volatile memory cell cross-point array. A first voltage is applied across a first group of memory cells for the operation and a lower second voltage is applied across other groups of memory cells. The first voltage is then applied across a second group of memory cells while the second voltage is applied across the other groups including the first group of memory cells and repeated until the operations covers all the groups.

Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

Abstract: A memory architecture for 3-dimensional thyristor cell arrays is disclosed. Thyristor memory cells are connected in a 3-dimensional cross-point array to form a bit line cluster. The bit line clusters are connected in parallel to sense amplifier and write circuits through multiplexer/demultiplexer circuits. Control circuits select one of the bit line clusters during a read or write operation while the non-selected bit line clusters are not activated to avoid disturbs and power consumption in the non-selected bit line clusters. The bit line clusters, multiplexer/demultiplexer circuits, and sense amplifier and write circuits from a memory array tile (MAT).

Abstract: A memory device may include a local bit line electrically coupled to a plurality of memory cells and a global bit line electrically coupled to the local bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path may be active and the second path may be in an off state in at least one of a set operation or a forming operation. The second path may be active in a reset operation, wherein the second impedance of the second path has a lower impedance than the first impedance of the first path.

Abstract: Aspects of DDR and thyristor memory cell RAMs are optimally combined for high-speed data transfer into and out of RAMs. After a Read operation in which data from a selected row of memory cells in an array are latched, a Burst operation selectively moves the latched data from the array or latches external data. At the same time as the Burst data transfer, all the memory cells of the selected row are turned off or on by a write operation. In the following Write-Back & Pre-charge operation, the latched data bits which are complementary to the memory cell state of the Burst write operation are written back into the corresponding memory cells in the selected row. As part of a DDR-like activation cycle, data can be transferred to and from the memory cell array RAM at high-speed.

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.

Abstract: A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

Abstract: Single thyristor memory cells form a volatile memory array. A sense amplifier reads the state of the thyristor in a selected memory cell against a dummy cell through precharged lines.

Abstract: Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled for an operation on a set of memory cells in an array, sequentially engaging subsets of memory cells for the operation while keeping the remaining memory cells of the set on hold until all the memory cells of the set have been operated on.

Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

Abstract: A memory device includes a local bit line coupled to a plurality of memory cells and a global bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path is active in at least one of a set operation or a forming operation and the second path is active in a reset operation. A select device to select a memory element includes a drain having a first doping level and a source having a second doping level lower than the first doping level, wherein the device is configured to provide a first on impedance or a second on impedance to the resistive memory element in response to a control signal.