Abstract: Accelerator access control whereby an application's access to an accelerator is revoked in order to allow the system to perform a system function. In one or more embodiments, when an application is executing, a credit system is utilized to provide credits for controlled access to the accelerator. When request information is received to remove access to a credit associated with the application's access to the accelerator, the credit is marked to fail with operating system interfaces. Also, in one or more embodiments, if the credit is in use for accessing the accelerator, an effective address associated with the credit is unmapped from the accelerator.

Abstract: Accelerator access control whereby an application's access to an accelerator is revoked in order to allow the system to perform a system function. In one or more embodiments, when an application is executing, a credit system is utilized to provide credits for controlled access to the accelerator. When request information is received to remove access to a credit associated with the application's access to the accelerator, the credit is marked to fail with operating system interfaces. Also, in one or more embodiments, if the credit is in use for accessing the accelerator, an effective address associated with the credit is unmapped from the accelerator.

Abstract: A digital computing system is configured to control access to an accelerator. The system includes a processor that executes an application, and an accelerator that performs a data processing operation in response to an access request output from the application. The system further includes a virtual accelerator switchboard (VAS) to determine an availability of at least one shared credit corresponding to the accelerator and assign an available shared credit to the application. The application submits a request to access the accelerator using the assigned shared credit.

Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.

Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.

Abstract: Improved techniques for memory expansion are provided. A storage volume is opened on a storage device attached to a computing system, and the storage volume is configured as extended memory. A number of hardware threads available in the computing system are determined, and a number of contexts equal to the determined number of hardware threads are generated. Each context is assigned to one of the hardware threads. It is further determined that a first hardware thread has requested a first page that has been paged to the storage volume, where the first hardware thread is assigned a first context. A synchronous input output (I/O) interface is accessed to request that the first page be moved to memory, based on the first context. While the first page is being moved to memory, a priority of the first hardware thread is reduced.

Abstract: Accelerator access control whereby an application's access to an accelerator is revoked in order to allow the system to perform a system function. In one or more embodiments, when an application is executing, a credit system is utilized to provide credits for controlled access to the accelerator. When request information is received to remove access to a credit associated with the application's access to the accelerator, the credit is marked to fail with operating system interfaces. Also, in one or more embodiments, if the credit is in use for accessing the accelerator, an effective address associated with the credit is unmapped from the accelerator.

Abstract: A digital computing system is configured to control access to an accelerator. The system includes a processor that executes an application, and an accelerator that performs a data processing operation in response to an access request output from the application. The system further includes a virtual accelerator switchboard (VAS) to determine an availability of at least one shared credit corresponding to the accelerator and assign an available shared credit to the application. The application submits a request to access the accelerator using the assigned shared credit.

Abstract: A method, program product, and system is provided for dynamic virtual processor management in a computer having a plurality of concurrent multi-threaded physical processors. An active logical partition is assigned to one of a plurality of shared processor pools, each shared processor pool having a virtual processor manager mode. A target performance metric for a workload in the active logical partition is compared to a calculated CPU utilization ratio or a calculated response time ratio. The workload in the active logical partition is dynamically moved from the assigned shared processor pool to a logical partition in another of the plurality of shared processor pools based on the target performance metric not being met in the active logical partition, and wherein the logical partition in another of the plurality of shared processor pools is configured to meet the target performance metric.

Abstract: Improved techniques for memory expansion are provided. A storage volume is opened on a storage device attached to a computing system, and the storage volume is configured as extended memory. A number of hardware threads available in the computing system are determined, and a number of contexts equal to the determined number of hardware threads are generated. Each context is assigned to one of the hardware threads. It is further determined that a first hardware thread has requested a first page that has been paged to the storage volume, where the first hardware thread is assigned a first context. A synchronous input output (I/O) interface is accessed to request that the first page be moved to memory, based on the first context. While the first page is being moved to memory, a priority of the first hardware thread is reduced.

Abstract: Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

Abstract: A method for zeroing memory in computing systems where access to memory is non-uniform includes receiving, via a system call, a request to delete a memory region, forwarding the request to an intermediate software thread, and using the intermediate software thread to perform the request as a background process. The method further includes, upon receiving a message from the intermediate software thread, returning to a system caller, while performing the request, via the intermediate software thread, continues in the background.

Abstract: A method for zeroing memory in computing systems where access to memory is non-uniform includes receiving, via a system call, a request for a pool of memory, determining a size of the requested pool of memory, and creating a dummy memory segment. The size of the dummy memory segment is larger than the size of the requested pool of memory. The dummy memory segment is filled with one or more pages, based on the determined size of the requested pool of memory, and the dummy memory segment is deleted.

Abstract: A method for zeroing memory in computing systems where access to memory is non-uniform includes receiving, via a system call, a request for a pool of memory, determining a size of the requested pool of memory, and creating a dummy memory segment. The size of the dummy memory segment is larger than the size of the requested pool of memory. The dummy memory segment is filled with one or more pages, based on the determined size of the requested pool of memory, and the dummy memory segment is deleted.

Abstract: A method, program product, and system is provided for dynamic virtual processor management in a computer having a plurality of concurrent multi-threaded physical processors. An active logical partition is assigned to one of a plurality of shared processor pools, each shared processor pool having a virtual processor manager mode. A target performance metric for a workload in the active logical partition is compared to a calculated CPU utilization ratio or a calculated response time ratio. The workload in the active logical partition is dynamically moved from the assigned shared processor pool to a logical partition in another of the plurality of shared processor pools based on the target performance metric not being met in the active logical partition, and wherein the logical partition in another of the plurality of shared processor pools is configured to meet the target performance metric.

Abstract: Systems, methods, and computer program products to perform an operation comprising creating, by a kernel, a temporary effective address associated with a virtual segment identifier (VSID), wherein the VSID is received by a processor in an asynchronous interrupt generated by a coherent accelerator in response to a page fault generated by the coherent accelerator in executing an instruction, accessing the temporary effective address by the processor to recreate the page fault on the processor, and resolving the page fault by an operating system executing on the processor.

Abstract: A method, program product, and system is provided for dynamic virtual processor management in a computer having a plurality of concurrent multi-threaded physical processors. A workload is assigned to a first virtual processor manager pool based on a virtual processor manager mode of the first virtual processor manager pool. A current utilization ratio and a response time ratio for the workload are calculated. The workload is dynamically moved to a second virtual processor manager pool based on either the current utilization ratio or the response time ratio exceeding a configurable threshold. The workload is dynamically moved between virtual processor manager pools to realize target performance metric requirements.

Abstract: A method for zeroing memory in computing systems where access to memory is non-uniform includes receiving, via a system call, a request to delete a memory region. The method also includes sorting, after receiving the request, one or more pages of the memory region according to each associated affinity domain of each page. The method further includes sending requests to zero the sorted one or more pages to one or more zeroing threads that are attached to the respective affinity domain. The method further yet includes waiting, after sending the requests, to return to the system caller until a message is received, from the zeroing threads in each affinity domain, indicating that all the page zeroing requests have been processed.

Abstract: Embodiments disclosed herein generally relate to techniques for zeroing memory in computing systems where access to memory is non-uniform. One embodiment provides a method which includes receiving, via a system call, a request to delete a memory region. The method also includes forwarding the request to an intermediate software thread, and using the intermediate software thread to perform the request as a background process. The method further includes, upon receiving a message from the intermediate software thread, returning to a system caller, while performing the request, via the intermediate software thread, continues in the background.

Abstract: Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.