Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.

Abstract: Embodiments disclosed herein generally relate to techniques for zeroing memory in computing systems where access to memory is non-uniform. One embodiment provides a method. The method generally includes receiving, via a system call, a request for a pool of memory. The method also includes determining a size of the requested pool of memory, and creating a dummy memory segment. The size of the dummy memory segment is larger than the size of the requested pool of memory. The method further includes filling the dummy memory segment with one or more pages, based on the determined size of the requested pool of memory, and deleting the dummy memory segment.

Abstract: Embodiments disclosed herein generally relate to techniques for zeroing memory in computing systems where access to memory is non-uniform. One embodiment provides a method. The method generally includes receiving, via a system call, a request for a pool of memory. The method also includes determining a size of the requested pool of memory, and creating a dummy memory segment. The size of the dummy memory segment is larger than the size of the requested pool of memory. The method further includes filling the dummy memory segment with one or more pages, based on the determined size of the requested pool of memory, and deleting the dummy memory segment.

Abstract: Systems, methods, and computer program products to perform an operation comprising determining, by a processor, a process identifier of a process associated with a page fault based on an interrupt source number, wherein the page fault was triggered by a coherent accelerator, executing the process on the processor to recreate the page fault on the processor, and resolving the page fault by an operating system executing on the processor.

Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.

Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.

Abstract: A system includes a processor and a memory storing a program, and a computer readable medium includes a program for performing an operation for zeroing memory in computing systems where access to memory is non-uniform. The operation includes receiving, via a system call, a request to delete a memory region. The operation also includes sorting, after receiving the request, one or more pages of the memory region according to each associated affinity domain of each page. The operation further includes sending requests to zero the sorted one or more pages to one or more zeroing threads that are attached to the respective affinity domain. The operation further yet includes waiting, after sending the requests, to return to the system caller until a message is received, from the zeroing threads in each affinity domain, indicating that all the page zeroing requests have been processed.

Abstract: A technique for handling interrupts in a data processing system includes maintaining, at an interrupt presentation controller (IPC), an interrupt acknowledge count (IAC). The IAC provides an indication of a number of times a virtual processor thread implemented at a first software stack level has been interrupted in response to receipt of event notification messages (ENMs) from an interrupt source controller (ISC). In response to the IAC reaching a threshold level, the IPC transmits an escalate message to the ISC. The escalate message includes an escalate event number that is used by the ISC to generate a new ENM that targets a second software stack level that is different than the first software stack level and is associated with another virtual processor thread.

Abstract: Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

Abstract: A method for zeroing memory in computing systems where access to memory is non-uniform includes receiving, via a system call, a request to delete a memory region. The method also includes forwarding the request to an intermediate software thread, and using the intermediate software thread to perform the request as a background process. The method further includes, upon receiving a message from the intermediate software thread, returning to a system caller, while performing the request, via the intermediate software thread, continues in the background.

Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.

Abstract: The present disclosure relates to sharing a context on a coherent hardware accelerator among multiple processes. According to one embodiment, in response to a first process requesting to create a shared memory space, a system creates a shared hardware context on the coherent hardware accelerator and binds the first process and the shared memory space to the hardware context. In response to the first process spawning one or more second processes, the system binds the one or more second processes to the shared memory space and the hardware context. Subsequently, the system performs one or more operations initiated by the first process or one of the one or more second processes on the coherent hardware accelerator according to the bound hardware context.

Abstract: A system includes a processor and a memory storing a program, and a computer readable medium includes a program for zeroing memory in computing systems where access to memory is non-uniform. When executed on a processor, the program causes the processor to perform an operation that includes receiving, via a system call, a request for a pool of memory. The operation also includes determining a size of the requested pool of memory, and creating a dummy memory segment. The size of the dummy memory segment is larger than the size of the requested pool of memory. The operation further includes filling the dummy memory segment with one or more pages, based on the determined size of the requested pool of memory, and deleting the dummy memory segment.

Abstract: A method for zeroing memory in computing systems where access to memory is non-uniform includes receiving, via a system call, a request for a pool of memory. The method also includes determining a size of the requested pool of memory, and creating a dummy memory segment. The size of the dummy memory segment is larger than the size of the requested pool of memory. The method further includes filling the dummy memory segment with one or more pages, based on the determined size of the requested pool of memory, and deleting the dummy memory segment.

Abstract: A method is provided for prioritized hardware thread scheduling. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.

Abstract: A computer program product is provided for prioritized hardware thread scheduling. The computer program product includes a non-transitory computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a computer to cause the computer to perform a method. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.

Abstract: Embodiments disclose techniques for enabling the use poll and select subroutines with coherent accelerator block or character devices. In one embodiment, an operating system receives, from an application, a system call to attach a hardware context with the coherent accelerator block or character device. The operating system generates a channel based on a file descriptor associated with the attach system call. The operating system associates the channel with a hardware context selected from a plurality of hardware contexts available to the coherent accelerator, wherein the hardware context is attached to the application. Upon receiving, from the application, a system call to check for exceptions that have occurred on the coherent accelerator block device or character device, the operating system returns an indication of any exceptions which have occurred while the coherent accelerator was using the hardware context to the application.

Abstract: Embodiments disclose techniques for emulating memory mapped I/O (MMIO) for coherent accelerators in an error state. In one embodiment, once an operating system determines that a processor is unable to access a coherent accelerator via a MMIO operation, the operating system deletes one or more page table entries associated with MMIO of one or more hardware contexts of the coherent accelerator. After deleting the page table entries, the operating system can detect a page fault associated with execution of a process by the processor. Upon determining that the page fault was caused by the process attempting to access one of the deleted page table entries while executing a MMIO operation, the operating system emulates the execution of the MMIO operation for the faulting process, giving the process the illusion that its requested MMIO operation was successful.

Abstract: Embodiments disclose techniques for enabling the use poll and select subroutines with coherent accelerator block or character devices. In one embodiment, an operating system receives, from an application, a system call to attach a hardware context with the coherent accelerator block or character device. The operating system generates a channel based on a file descriptor associated with the attach system call. The operating system associates the channel with a hardware context selected from a plurality of hardware contexts available to the coherent accelerator, wherein the hardware context is attached to the application. Upon receiving, from the application, a system call to check for exceptions that have occurred on the coherent accelerator block device or character device, the operating system returns an indication of any exceptions which have occurred while the coherent accelerator was using the hardware context to the application.

Abstract: The present disclosure relates to sharing a context on a coherent hardware accelerator among multiple processes. According to one embodiment, in response to a first process requesting to create a shared memory space, a system creates a shared hardware context on the coherent hardware accelerator and binds the first process and the shared memory space to the hardware context. In response to the first process spawning one or more second processes, the system binds the one or more second processes to the shared memory space and the hardware context. Subsequently, the system performs one or more operations initiated by the first process or one of the one or more second processes on the coherent hardware accelerator according to the bound hardware context.