Patents by Inventor Bunji Mizuno

Bunji Mizuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8105926
    Abstract: A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: January 31, 2012
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Keiichi Nakamoto, Hiroyuki Ito, Bunji Mizuno
  • Publication number: 20120015504
    Abstract: A semiconductor device includes: a first semiconductor region formed on a substrate and having an upper surface and a side surface; a first impurity region of a first conductivity type formed in an upper portion of the first semiconductor region; a second impurity region of a first conductivity type formed in a side portion of the first semiconductor region; and a gate insulating film formed so as to cover at least a side surface and an upper corner of a predetermined portion of the first semiconductor region. A radius of curvature r? of an upper corner of a portion of the first semiconductor region located outside the gate insulating film is greater than a radius of curvature r of an upper corner of a portion of the first semiconductor region located under the gate insulating film and is less than or equal to 2r.
    Type: Application
    Filed: September 26, 2011
    Publication date: January 19, 2012
    Applicant: Panasonic Corporation
    Inventors: Yuichiro SASAKI, Katsumi Okashita, Keiichi Nakamoto, Hisataka Kanada, Bunji Mizuno
  • Patent number: 8063437
    Abstract: A semiconductor device includes: a first semiconductor region formed on a substrate and having an upper surface and a side surface; a first impurity region of a first conductivity type formed in an upper portion of the first semiconductor region; a second impurity region of a first conductivity type formed in a side portion of the first semiconductor region; and a gate insulating film formed so as to cover at least a side surface and an upper corner of a predetermined portion of the first semiconductor region. A radius of curvature r? of an upper corner of a portion of the first semiconductor region located outside the gate insulating film is greater than a radius of curvature r of an upper corner of a portion of the first semiconductor region located under the gate insulating film and is less than or equal to 2r.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: November 22, 2011
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Keiichi Nakamoto, Hisataka Kanada, Bunji Mizuno
  • Publication number: 20110272763
    Abstract: Extension regions (17) are provided in side portions of a fin-shaped semiconductor region (13) formed on a substrate (11). A gate electrode (15) is formed to extend across the fin-shaped semiconductor region (13) and to be adjacent to the extension regions (17). A resistance region (37) having a resistivity higher than that of the extension regions (17) is formed in an upper portion of the fin-shaped semiconductor region (13) adjacent to the gate electrode (15).
    Type: Application
    Filed: December 17, 2009
    Publication date: November 10, 2011
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Bunji Mizuno
  • Publication number: 20110275201
    Abstract: First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r1? of the upper corner of the first fin-shaped semiconductor region located outside the first gate insulating film is greater than the radius of curvature r1 of the upper corner of the first fin-shaped semiconductor region located under the first gate insulating film and is less than or equal to 2×r1. The radius of curvature r2? of the upper corner of the second fin-shaped semiconductor region located outside the second gate insulating film is greater than the radius of curvature r2 of the upper corner of the second fin-shaped semiconductor region located under the second gate insulating film and is less than or equal to 2×r2.
    Type: Application
    Filed: July 18, 2011
    Publication date: November 10, 2011
    Applicant: Panasonic Corporation
    Inventors: Yuichiro SASAKI, Keiichi Nakamoto, Katsumi Okashita, Hisataka Kanada, Bunji Mizuno
  • Patent number: 8030187
    Abstract: A substrate is exposed to a plasma generated from a gas containing an impurity, thereby doping a surface portion of the substrate with the impurity and thus forming an impurity region. A predetermined plasma doping time is used, which is included within a time range over which a deposition rate on the substrate by the plasma is greater than 0 nm/min and less than or equal to 5 nm/min.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: October 4, 2011
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Keiichi Nakamoto, Bunji Mizuno
  • Publication number: 20110237056
    Abstract: An object of this invention is to provide a method for making a junction which is simple in the process, high in the throughput, and can make a shallow junction with high accuracy. After the suitable state of a substrate surface adapted to the wavelength of an electromagnetic wave to be applied has been formed, the electromagnetic wave is applied to electrically activate impurities so that the excited energy is effectively absorbed within the impurity thin film, thereby effectively making a shallow junction.
    Type: Application
    Filed: June 7, 2011
    Publication date: September 29, 2011
    Applicant: Panasonic Corporation
    Inventors: Yuichiro SASAKI, Cheng-Guo JIN, Bunji MIZUNO
  • Publication number: 20110217830
    Abstract: There are provided a plasma doping method and an apparatus which have excellent reproducibility of the concentration of impurities implanted into the surfaces of samples. In a vacuum container, in a state where gas is ejected toward a substrate placed on a sample electrode through gas ejection holes provided in a counter electrode, gas is exhausted from the vacuum container through a turbo molecular pump as an exhaust device, and the inside of the vacuum container is maintained at a predetermined pressure through a pressure adjustment valve, the distance between the counter electrode and the sample electrode is set to be sufficiently small with respect to the area of the counter electrode to prevent plasma from being diffused outward, and capacitive-coupled plasma is generated between the counter electrode and the sample electrode to perform plasma doping. The gas used herein is a gas with a low concentration which contains impurities such as diborane or phosphine.
    Type: Application
    Filed: May 16, 2011
    Publication date: September 8, 2011
    Applicant: Panasonic Corporation
    Inventors: Tomohiro OKUMURA, Yuichiro Sasaki, Katsumi Okashita, Hiroyuki Ito, Bunji Mizuno
  • Patent number: 8012862
    Abstract: A fin-shaped semiconductor region is formed on a substrate, and then the substrate is placed in a chamber. Then, an ignition gas is introduced into a chamber to thereby turn the ignition gas into a plasma, and then a process gas containing an impurity is introduced into the chamber to thereby turn the process gas into a plasma. Then, a bias voltage is applied to the substrate so as to dope the semiconductor region with the impurity after confirming attenuation of an amount of the ignition gas remaining in the chamber.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: September 6, 2011
    Assignee: Panasonic Corporation
    Inventors: Katsumi Okashita, Yuichiro Sasaki, Keiichi Nakamoto, Bunji Mizuno
  • Patent number: 8004045
    Abstract: First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r1? of the upper corner of the first fin-shaped semiconductor region located outside the first gate insulating film is greater than the radius of curvature r1 of the upper corner of the first fin-shaped semiconductor region located under the first gate insulating film and is less than or equal to 2×r1. The radius of curvature r2? of the upper corner of the second fin-shaped semiconductor region located outside the second gate insulating film is greater than the radius of curvature r2 of the upper corner of the second fin-shaped semiconductor region located under the second gate insulating film and is less than or equal to 2×r2.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: August 23, 2011
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Keiichi Nakamoto, Katsumi Okashita, Hisataka Kanada, Bunji Mizuno
  • Patent number: 7981779
    Abstract: An object of this invention is to provide a method for making a junction which is simple in the process, high in the throughput, and can make a shallow junction with high accuracy. After the suitable state of a substrate surface adapted to the wavelength of an electromagnetic wave to be applied has been formed, the electromagnetic wave is applied to electrically activate impurities so that the excited energy is effectively absorbed within the impurity thin film, thereby effectively making a shallow junction.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: July 19, 2011
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Cheng-Guo Jin, Bunji Mizuno
  • Patent number: 7972945
    Abstract: A top plate, disposed on an upper portion of a vacuum container so as to face a substrate-placing area of a sample electrode, is provided with an impurity-containing film that contains an impurity, and is formed on a top plate peripheral edge portion area that is a face exposable to a plasma generated in the vacuum container, and is located on a peripheral edge of a top plate center portion area that faces the center portion of the substrate-placing area.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: July 5, 2011
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Bunji Mizuno
  • Publication number: 20110151652
    Abstract: An impurity is introduced into a fin-type semiconductor region (102) formed on a substrate (100) using a plasma doping process, thereby forming an impurity-introduced layer (105). Carbon is introduced into the fin-type semiconductor region (102) using a plasma doping process to overlap at least a part of the impurity-introduced layer (105), thereby forming a carbon-introduced layer.
    Type: Application
    Filed: March 26, 2010
    Publication date: June 23, 2011
    Inventors: Yuichiro Sssaki, Katsumi Okashita, Bunji Mizuno
  • Publication number: 20110147813
    Abstract: A method for fabricating a semiconductor device includes: forming a fin-type semiconductor region on a substrate; and introducing an n-type impurity into at least a side of the fin-type semiconductor region by a plasma doping process, thereby forming an n-type impurity region in the side of the fin-type semiconductor region. In the introducing the n-type impurity, when a source power in the plasma doping process is denoted by a character Y [W], the supply of a gas containing the n-type impurity per unit time and per unit volume is set greater than or equal to 5.1×10?8/(1.72.51/24.51)×(Y/500)) [mol/(min·L·sec)], and the supply of a diluent gas per unit time and per unit volume is set greater than or equal to 1.7×10?4(202.51/24.51)×(Y/500)) [mol/(min·L·sec)].
    Type: Application
    Filed: November 11, 2010
    Publication date: June 23, 2011
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Bunji Mizuno
  • Publication number: 20110147856
    Abstract: A fin-type semiconductor region (103) is formed on a substrate (101), and then a resist pattern (105) is formed on the substrate (101). An impurity is implanted into the fin-type semiconductor region (103) by a plasma doping process using the resist pattern (105) as a mask, and then at least a side of the fin-type semiconductor region (103) is covered with a protective film (107). Thereafter, the resist pattern (105) is removed by cleaning using a chemical solution, and then the impurity implanted into the fin-type semiconductor region (103) is activated by heat treatment.
    Type: Application
    Filed: March 4, 2010
    Publication date: June 23, 2011
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Bunji Mizuno
  • Patent number: 7939388
    Abstract: Before a plasma doping process is performed, there is generated a plasma of a gas containing an element belonging to the same group in the periodic table as the primary element of a silicon substrate 9, e.g., a monosilane gas, in a vacuum chamber 1. Thus, the inner wall of the vacuum chamber 1 is covered with a silicon-containing film. Then, a plasma doping process is performed on the silicon substrate 9.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: May 10, 2011
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Okumura, Hisao Nagai, Yuichiro Sasaki, Katsumi Okashita, Hiroyuki Ito, Bunji Mizuno
  • Patent number: 7932185
    Abstract: A laser annealing process capable of suppressing a variation in sheet resistance. A surface layer formed shallower than 100 nm in a substrate of semiconductor material is added with impurities. The substrate is irradiated with a laser beam or its harmonic beam emitted from a laser diode pumped to solid-state laser to activate the impurities.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: April 26, 2011
    Assignees: Sumitomo Heavy Industries, Ltd., Panasonic Corporation
    Inventors: Toshio Kudo, Bunji Mizuno, Yuichiro Sasaki, Cheng-Guo Jin
  • Publication number: 20110081787
    Abstract: With evacuation of interior of a vacuum chamber halted and with gas supply into the vacuum chamber halted, in a state that a mixed gas of helium gas and diborane gas is sealed in the vacuum chamber, a plasma is generated in a vacuum vessel and simultaneously a high-frequency power is supplied to a sample electrode. By the high-frequency power supplied to the sample electrode, boron is introduced to a proximity to the substrate surface.
    Type: Application
    Filed: November 19, 2010
    Publication date: April 7, 2011
    Inventors: Tomohiro OKUMURA, Ichiro Nakayama, Satoshi Maeshima, Bunji Mizuno, Yuichiro Sasaki
  • Publication number: 20110065267
    Abstract: In order to realize a plasma doping method capable of carrying out a stable low-density doping, exhaustion is carried out with a pump while introducing a predetermined gas into a vacuum chamber from a gas supplying apparatus, the pressure of the vacuum chamber is held at a predetermined pressure and a high frequency power is supplied to a coil from a high frequency power source. After the generation of plasma in the vacuum chamber, the pressure of the vacuum chamber is lowered, and the low-density plasma doping is performed to a substrate placed on a substrate electrode. Moreover, the pressure of the vacuum chamber is gradually lowered, and the high frequency power is gradually increased, thereby the low-density plasma doping is carried out to the substrate placed on the substrate electrode.
    Type: Application
    Filed: November 23, 2010
    Publication date: March 17, 2011
    Applicant: Panasonic Corporation
    Inventors: Tomohiro Okumura, Ichiro Nakayama, Bunji Mizuno, Yuichiro Sasaki
  • Publication number: 20110065266
    Abstract: A substrate is exposed to a plasma generated from a gas containing an impurity, thereby doping a surface portion of the substrate with the impurity and thus forming an impurity region. A predetermined plasma doping time is used, which is included within a time range over which a deposition rate on the substrate by the plasma is greater than 0 nm/min and less than or equal to 5 nm/min.
    Type: Application
    Filed: September 3, 2008
    Publication date: March 17, 2011
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Keiichi Nakamoto, Bunji Mizuno