Patents by Inventor Bunji Mizuno

Bunji Mizuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7888937
    Abstract: A beam current sensor is composed of a cylindrical super-conductive body having a bridge unit formed on the outer diameter side wherein a beam passes through the inner diameter side. The sensor improves efficiency of creating a magnetic field from a current and can measure a beam current as 1 nA. The bridge unit includes a first coil unit formed so as to have an eddy shape wound counterclockwise from the outer diameter side toward the inner diameter side; a second coil unit formed so as to have an eddy shape wound clockwise from the outer diameter side toward the inner diameter side; and a connection portion for connecting the center position of the inner diameter side of the first coil unit with the center position of the inner diameter side of the second coil.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: February 15, 2011
    Assignees: Riken, Panasonic Corporation
    Inventors: Tamaki Watanabe, Takeshi Katayama, Masayuki Kase, Tokihiro Ikeda, Shin-ichi Watanabe, Takeo Kawaguchi, Yu-ichiro Sasaki, Bunji Mizuno, Hisataka Kanada
  • Patent number: 7871853
    Abstract: A plasma doping method and a plasma doping apparatus, having a superior in-plane uniformity of an amorphous layer formed on a sample surface, are provided. In the plasma doping method by which plasma is generated within a vacuum chamber, and impurity ions contained in the plasma are caused to collide with the surface of the sample so as to quality-change the surface of the sample into an amorphous state thereof, a plasma irradiation time is adjusted in order to improve an in-plane uniformity. If the plasma irradiation time becomes excessively short, then a fluctuation of the plasma is transferred to depths of an amorphous layer formed on a silicon substrate, so that the in-plane uniformity is deteriorated. On the other hand, if the irradiation time becomes excessively long, then an effect for sputtering the surface of the silicon substrate by using the plasma becomes dominant, then the in-plane uniformity is deteriorated.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: January 18, 2011
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Hiroyuki Ito, Bunji Mizuno
  • Patent number: 7863168
    Abstract: In order to realize a plasma doping method capable of carrying out a stable low-density doping, exhaustion is carried out with a pump while introducing a predetermined gas into a vacuum chamber from a gas supplying apparatus, the pressure of the vacuum chamber is held at a predetermined pressure and a high frequency power is supplied to a coil from a high frequency power source. After the generation of plasma in the vacuum chamber, the pressure of the vacuum chamber is lowered, and the low-density plasma doping is performed to a substrate placed on a substrate electrode. Moreover, the pressure of the vacuum chamber is gradually lowered, and the high frequency power is gradually increased, thereby the low-density plasma doping is carried out to the substrate placed on the substrate electrode.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: January 4, 2011
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Okumura, Ichiro Nakayama, Bunji Mizuno, Yuichiro Sasaki
  • Publication number: 20100330782
    Abstract: A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region.
    Type: Application
    Filed: August 10, 2010
    Publication date: December 30, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Yuichiro SASAKI, Katsumi OKASHITA, Keiichi NAKAMOTO, Hiroyuki ITO, Bunji MIZUNO
  • Patent number: 7858537
    Abstract: With evacuation of interior of a vacuum chamber halted and with gas supply into the vacuum chamber halted, in a state that a mixed gas of helium gas and diborane gas is sealed in the vacuum chamber, a plasma is generated in a vacuum vessel and simultaneously a high-frequency power is supplied to a sample electrode. By the high-frequency power supplied to the sample electrode, boron is introduced to a proximity to the substrate surface.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: December 28, 2010
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Okumura, Ichiro Nakayama, Satoshi Maeshima, Bunji Mizuno, Yuichiro Sasaki
  • Patent number: 7858155
    Abstract: It is intended to provide a plasma processing method and apparatus capable of increasing the uniformity of amorphyzation processing. A prescribed gas is introduced into a vacuum container 1 from a gas supply apparatus 2 through a gas inlet 11 while being exhausted by a turbomolecular pump 3 as an exhaust apparatus through an exhaust hole 12. The pressure in the vacuum container 1 is kept at a prescribed value by a pressure regulating valve 4. High-frequency electric power of 13.56 MHz is supplied from a high-frequency power source 5 to a coil 8 disposed close to a dielectric window 7 which is opposed to a sample electrode 6, whereby induction-coupled plasma is generated in the vacuum container 1. A high-frequency power source 10 for supplying high-frequency electric power to the sample electrode 6 is provided and functions as a voltage source for controlling the potential of the sample electrode 6.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: December 28, 2010
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Okumura, Yuichiro Sasaki, Katsumi Okashita, Cheng-Guo Jin, Satoshi Maeshima, Hiroyuki Ito, Ichiro Nakayama, Bunji Mizuno
  • Patent number: 7858479
    Abstract: An object is to provide a semiconductor device in which uniform properties are intended and high yields are provided. Process steps are provided in which variations are adjusted in doping and annealing process steps that are subsequent process steps so as to cancel in-plane variations in a substrate caused by dry etching to finally as well provide excellent in-plane consistency in a substrate.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: December 28, 2010
    Assignee: Panasonic Corporation
    Inventors: Bunji Mizuno, Yuichiro Sasaki, Ichiro Nakayama, Hiroyuki Ito, Tomohiro Okumura, Cheng-Guo Jin, Katsumi Okashita, Hisataka Kanada
  • Publication number: 20100297836
    Abstract: A top plate, disposed on an upper portion of a vacuum container so as to face a substrate-placing area of a sample electrode, is provided with an impurity-containing film that contains an impurity, and is formed on a top plate peripheral edge portion area that is a face exposable to a plasma generated in the vacuum container, and is located on a peripheral edge of a top plate center portion area that faces the center portion of the substrate-placing area.
    Type: Application
    Filed: December 11, 2008
    Publication date: November 25, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Bunji Mizuno
  • Patent number: 7820230
    Abstract: An amount of leakage of a substrate-cooling gas into a vacuum container is measured by using a flow-rate measuring device so that the flow rate of a diluting gas that is the same as the substrate-cooling gas is controlled by a control device or a plasma doping time is prolonged, in accordance with the amount of leakage.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: October 26, 2010
    Assignee: Panasonic Corporation
    Inventors: Keiichi Nakamoto, Yuichiro Sasaki, Katsumi Okashita, Bunji Mizuno
  • Patent number: 7813946
    Abstract: The commodity recycling method of the present invention includes the steps of: selling or renting a commodity to a first user (step S1); collecting the commodity from the first user (step S2); estimating a remaining life of the commodity based on information indicating a usage history of the commodity recorded in a recording section provided in the commodity (step S3); determining sale terms or lease terms based on the estimated remaining life of the commodity (step S4); selling or renting the commodity to a second user in accordance with the sale terms or the lease terms (step S5). The recording section records the information indicating the usage history of the commodity in a manner in which it is substantially impossible for a user of the commodity to alter the usage history information.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: October 12, 2010
    Assignee: Panasonic Corporation
    Inventors: Bunji Mizuno, Toru Fukumoto, Shinichi Yamamoto, Junichi Onoue
  • Publication number: 20100255615
    Abstract: A fin-shaped semiconductor region is formed on a substrate, and then the substrate is placed in a chamber. Then, an ignition gas is introduced into a chamber to thereby turn the ignition gas into a plasma, and then a process gas containing an impurity is introduced into the chamber to thereby turn the process gas into a plasma. Then, a bias voltage is applied to the substrate so as to dope the semiconductor region with the impurity after confirming attenuation of an amount of the ignition gas remaining in the chamber.
    Type: Application
    Filed: October 2, 2008
    Publication date: October 7, 2010
    Inventors: Katsumi Okashita, Yuichiro Sasaki, Keiichi Nakamoto, Bunji Mizuno
  • Patent number: 7800165
    Abstract: A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: September 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Keiichi Nakamoto, Hiroyuki Ito, Bunji Mizuno
  • Patent number: 7790586
    Abstract: An impurity region is formed in a surface of a substrate by exposing the substrate to a plasma generated from a gas containing an impurity in a vacuum chamber. In this process, a plasma doping condition is set with respect to a dose of the impurity to be introduced into the substrate so that a first one of doses in a central portion and in a peripheral portion of the substrate is greater than a second one of the doses during an initial period of doping, with the second dose becoming greater than the first dose thereafter.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: September 7, 2010
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Hiroyuki Ito, Bunji Mizuno
  • Publication number: 20100207211
    Abstract: A semiconductor device includes: a fin-type semiconductor region (13) formed on a substrate (11); a gate insulating film (14) formed so as to cover an upper surface and both side surfaces of a predetermined portion of the fin-type semiconductor region (13); a gate electrode (15) formed on the gate insulating film (14); and an impurity region (17) formed on both sides of the gate electrode (15) in the fin-type semiconductor region (13). An impurity blocking portion (15a) for blocking the introduction of impurities is provided adjacent both sides of the gate electrode (15) over an upper surface of the fin-type semiconductor region (13).
    Type: Application
    Filed: April 30, 2009
    Publication date: August 19, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Keiichi Nakamoto, Bunji Mizuno
  • Patent number: 7759254
    Abstract: A method of forming an impurity-introduced layer is disclosed. The method includes at least a step of forming a resist pattern on a principal face of a solid substrate such as a silicon substrate (S27); a step of introducing impurity into the solid substrate through plasma-doping in ion mode (S23), a step of removing a resist (S28), a step of cleaning metal contamination and particles attached to a surface of the solid substrate (S25a); a step of anneal (S26). The step of removing a resist (S28) irradiates the resist with oxygen-plasma or brings mixed solution of sulfuric acid and hydrogen peroxide water, or mixed solution of NH4OH, H2O2 and H2O into contact with the resist. The step of cleaning (S25a) brings mixed solution of sulfuric acid and hydrogen peroxide water, or mixed solution of NH4OH, H2O2 and H2O into contact with the principal face of the solid substrate.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: July 20, 2010
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Bunji Mizuno, Hiroyuki Ito, Cheng-Guo Jin, Hideki Tamura, Ichiro Nakayama, Tomohiro Okumura, Satoshi Maeshima
  • Patent number: 7754503
    Abstract: A plasma of a gas containing an impurity is produced through a discharge in a vacuum chamber, and a plurality of substrates are successively doped with the impurity by using the plasma, wherein a plasma doping condition of a subject substrate is adjusted based on an accumulated discharge time until the subject substrate is placed in the vacuum chamber.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: July 13, 2010
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Keiichi Nakamoto, Hiroyuki Ito, Bunji Mizuno
  • Publication number: 20100167508
    Abstract: A method for introducing impurities includes a step for forming an amorphous layer at a surface of a semiconductor substrate, and a step for forming a shallow impurity-introducing layer at the semiconductor substrate which has been made amorphous, and an apparatus used therefore. Particularly, the step for forming the amorphous layer is a step for irradiating plasma to the surface of the semiconductor substrate, and the step for forming the shallow impurity-introducing layer is a step for introducing impurities into the surface which has been made amorphous.
    Type: Application
    Filed: March 5, 2010
    Publication date: July 1, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Yuichiro Sasaki, Bunji Mizuno, Cheng-Guo Jin
  • Patent number: 7741199
    Abstract: A method for introducing impurities includes a step for forming an amorphous layer at a surface of a semiconductor substrate, and a step for forming a shallow impurity-introducing layer at the semiconductor substrate which has been made amorphous, and an apparatus used therefore. Particularly, the step for forming the amorphous layer is a step for irradiating plasma to the surface of the semiconductor substrate, and the step for forming the shallow impurity-introducing layer is a step for introducing impurities into the surface which has been made amorphous.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: June 22, 2010
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Bunji Mizuno, Cheng-Guo Jin
  • Publication number: 20100148323
    Abstract: A subject of the present invention is to realize an impurity doping not to bring about a rise of a substrate temperature. Another subject of the present invention is to measure optically physical properties of a lattice defect generated by the impurity doping step to control such that subsequent steps are optimized. An impurity doping method, includes a step of doping an impurity into a surface of a solid state base body, a step of measuring an optical characteristic of an area into which the impurity is doped, a step of selecting annealing conditions based on a measurement result to meet the optical characteristic of the area into which the impurity is doped, and a step of annealing the area into which the impurity is doped, based on the selected annealing conditions.
    Type: Application
    Filed: February 23, 2010
    Publication date: June 17, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Cheng-Guo Jin, Yuichiro Sasaki, Bunji Mizuno
  • Patent number: 7709362
    Abstract: A method for introducing impurities includes a step for forming an amorphous layer at a surface of a semiconductor substrate, and a step for forming a shallow impurity-introducing layer at the semiconductor substrate which has been made amorphous, and an apparatus used therefore. Particularly, the step for forming the amorphous layer is a step for irradiating plasma to the surface of the semiconductor substrate, and the step for forming the shallow impurity-introducing layer is a step for introducing impurities into the surface which has been made amorphous.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: May 4, 2010
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Bunji Mizuno, Cheng-Guo Jin