Abstract: A method of fabricating a multi-zone, short gate length thin film transistor is provided. Gate metal and a plurality of layers are deposited on a substrate. The layers include a gate insulator, a first semiconductor, a second semiconductor, and source contact metal. An insulator is deposited on the plurality of layers partially overlapping the gate electrode and masking part of the plurality of layers. Portions of the source contact metal not masked by the insulator are removed and the first and second semiconductors are diffused with dopants via a plasma. Sidewalls of the insulator and source metal contact are covered with an insulating layer. Portions of the second semiconductor not masked are removed by etching for a length of time to create undercuts below the insulator and extending under the source contact metal. The undercuts are filled with an insulating material and an external metal contact layer is deposited.

Abstract: A method is provided for fabricating an ultra short gate length thin film transistor. A plurality of layers is deposited on a substrate including a refractory metal and a first and second photosensitive material. The second material is sensitive to longer wavelength optical radiation than the first material and the first material is not soluble in chemicals used to develop or strip the second material. A source contact pattern is defined in the second material to mask the first photosensitive material. The first material is processed to produce an undercut of the first material with respect to the second material. A metal layer is deposited at a normal incidence on the second material and an exposed portion of the refractory metal. The second material is removed. Exposed portions of the refractory metal corresponding to the undercut of the first material are removed to form a gap in the refractory metal.

Abstract: A method is provided for fabricating an ultra short gate length thin film transistor. A plurality of layers is deposited on a substrate including a refractory metal and a first and second photosensitive material. The second material is sensitive to longer wavelength optical radiation than the first material and the first material is not soluble in chemicals used to develop or strip the second material. A source contact pattern is defined in the second material to mask the first photosensitive material. The first material is processed to produce an undercut of the first material with respect to the second material. A metal layer is deposited at a normal incidence on the second material and an exposed portion of the refractory metal. The second material is removed. Exposed portions of the refractory metal corresponding to the undercut of the first material are removed to form a gap in the refractory metal.

Abstract: A method is provided for fabricating a thin film transistor. An insulating and a metal gate contact layer are deposited on a substrate with the insulating layer being positioned between the gate contact layer and the substrate. A portion of the gate contact layer is selectively removed utilizing reactive ion etching incorporating a gas that etches the gate contact layer but not the insulating layer. A plurality of layers is deposited over a remaining portion of the gate contact layer and insulating layer, which include a gate insulating layer, a channel layer, and a metal film. A portion of the metal film is selectively removed utilizing reactive ion etching incorporating the gas that etches the metal film but not the channel layer. The insulating layer includes a high resistivity insulator that can be deposited at temperatures less than 400° C. and the channel layer is comprised of a metal oxide semiconductor.

Abstract: A method is provided for fabricating a thin film transistor. A plurality of layers is deposited on a substrate. The plurality of layers includes a conductive gate contact layer, a gate insulator layer, an undoped channel layer, an etch-stop layer, and a conductive contact layer. The etch-stop layer is positioned between the conductive contact layer and the undoped channel layer. A portion of the conductive contact layer is selectively removed while removal of a portion of the undoped channel layer is prevented by the etch-stop layer during the selective removal. A portion of the etch-stop layer is selectively removed and an exposed portion of the etch-stop layer is converted from a conductor to an insulator by oxidizing the exposed portion of the etch-stop layer in air. A portion of remaining layers of the plurality of layers is selectively removed to form the thin film transistor.

Abstract: A method is provided for fabricating a thin film transistor. A plurality of layers is deposited on a substrate. The plurality of layers includes a conductive gate contact layer, a gate insulator layer, an undoped channel layer, an etch-stop layer, and a conductive contact layer. The etch-stop layer is positioned between the conductive contact layer and the undoped channel layer. A portion of the conductive contact layer is selectively removed while removal of a portion of the undoped channel layer is prevented by the etch-stop layer during the selective removal. A portion of the etch-stop layer is selectively removed and an exposed portion of the etch-stop layer is converted from a conductor to an insulator by oxidizing the exposed portion of the etch-stop layer in air. A portion of remaining layers of the plurality of layers is selectively removed to form the thin film transistor.

Abstract: A thermal and electrical interconnect for heterojunction bipolar transistors is disclosed wherein the interconnect is essentially comprised of gold and in thermal and electrical contact with each of the interdigitated emitter fingers and is capable of transporting heat fluxes between 0.25-1.5 mW/&mgr;m2. The interconnect is electrodeposited to form a low-stress interface with the emitter finger, thereby increasing the lifetime and reliability of the transistor.

Abstract: A thermally stabilized cascode heterojunction bipolar transistor (TSC-HB) having the current and power generation regions in separate temperature zones, each transistor collector in a cold zone connected directly and individually to an emitter terminal of a corresponding transistor in a hot zone, thereby limiting the current available to the emitter of the transistor in the hot zone. Such an interconnection of transistors prevents the transistor in the hot zone from drawing more current from other transistor sources when increases in temperature occur. This achieves thermal stability and prevents the transistors from overheating and burning out.

Abstract: A thermal and electrical interconnect for heterojunction bipolar transistors is disclosed wherein the interconnect is essentially comprised of gold and in thermal and electrical contact with each of the interdigitated emitter fingers and is capable of transporting heat fluxes between 0.25-1.5 mW/&mgr;m2. The interconnect is electrodeposited to form a low-stress interface with the emitter finger, thereby increasing the lifetime and reliability of the transistor.

Abstract: Heterojunction bipolar transistors (130) with bases (138) including an etch stop element are disclosed. The preferred embodiment devices have Al.sub.x Ga.sub.1-x As emitters (140) and GaAs collectors (136) and bases (138) with In.sub.y Ga.sub.1-x As added to the bases (138) to stop chloride plasma etches.

Abstract: A heterojunction bipolar transistor power cell consisting of a plurality of parallel connected sub-cells arranged in a chevron type of configuration wherein the sub-cells are staggered relative to one another so that the base feed for an input signal can have an equal electrical distance to all of the base contacts while keeping the orientation of the respective emitter fingers of the sub-cells in the same direction. By offsetting the sub-cells in a first or vertical direction, the number of sub-cells that can be arranged in a second or horizontal direction can be increased for the same horizontal distance as a conventional "in-line" design while overcoming the signal distribution limitation of a "fish-bone" design.

Abstract: Structure and fabrication details are disclosed for AlGaAs/GaAs microwave HBTs having improved thermal stability during high power operation. The use of a thermal shunt joining emitter contacts of a multi-emitter HBT is shown to improve this thermal stability and eliminate "current-crush" effects. A significant reduction in thermal resistance of the disclosed devices is also achieved by spreading the generated heat over a large substrate area using thermal lens techniques in the thermal shunt. These improvements achieve thermally stable operation of AlGaAs/GaAs HBTs up to their electronic limitations. A power density of 10 mW/.mu.m2 of emitter area is achieved with 0.6 W CW output power and 60% power-added efficiency at 10 GHz. The thermal stabilization technique is applicable to other bipolar transistors including silicon, germanium, and indium phosphide devices.

Abstract: The durable mask includes a polyimide layer formed over a portion of a semiconductor substrate to be masked. A heavy metal layer is then formed over the polyimide layer. An adhesion layer is formed between the polyimide layer and the heavy metal layer to insure adhesion of the heavy metal layer to the polyimide layer. The durable mask may mask, for example, a heterojunction bipolar transistor formed in the semiconductor substrate prior to an ion implantation process. Furthermore, the mask is removed from the substrate by eliminating the adhesion between the mask and substrate or by dissolving the polyimide layer.

Abstract: Generally, and in one form of the invention, a microwave heterojunction bipolar transistor suitable for low-power, low-noise and high-power applications having an emitter 108, a base 126 and a collector 24 is disclosed, wherein the base 126 is composed of one or more islands 126 of semiconductor material. The one or more islands 126 are formed so that they do not cross any boundaries of the active area 60 of the transistor.

Abstract: Heterojunction bipolar transistors (130) with bases (138) including an etch stop element are disclosed. The preferred embodiment devices have Al.sub.z Ga.sub.1-z As emitters (140) and GaAs collectors (136) and bases (138) with In.sub.y Ga.sub.1-y As added to the bases (138) to stop chloride plasma etches.

Abstract: Generally, and in one form of the invention, a microwave heterojunction bipolar transistor suitable for low-power, low-noise and high-power applications having an emitter, a base 50 and a collector 70 is disclosed, wherein the emitter composed of one or more islands 30 of semiconductor material having a wider energy bandgap than the base 50. The islands 30 are formed so that they do not cross any boundaries of the active area 60 of the transistor.Other devices, systems and methods are also disclosed.

Abstract: A monolithic circuit including an IMPATT with the IMPATT formed as a plurality of parallel vertical fingers or an array of vertical mesas having a common doped region to apread the area for heat dissipation through the substrate.

Abstract: Preferred embodiments include a microstrip patch antenna (38) which also acts as the resonator for an oscillator powered by IMPATT diodes (34, 36); this forms a monolithic transmitter (30) for microwave and millimeter wave frequencies.

Abstract: Integrated circuits and fabrication methods incorporating both two-terminal devices such as IMPATT diodes (446) and Schottky diodes (454) and three-terminal devices such as n-channel MESFETs (480) in a monolithic integrated circuit.

Abstract: A method of fabricating heterojunction bipolar transistors (HBTs) including epitaxial growth of collector, base and emitter layers, allowing for self-aligned emitter-base contacts to minimize series base resistance and to reduce total base-collector capacitance.