Patents by Inventor Burnell G. West
Burnell G. West has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7765443Abstract: One embodiment of the invention is a portion of a test system that includes a timing generation circuit and a formatter that are coupled together, which are on a single CMOS (complementary metal oxide semiconductor) integrated circuit. The timing Generation circuit generates software words. The formatter receives the software words and provides a specified number of transitions per second and a specified edge placement resolution and accuracy. It is noted that the formatter includes a drive circuit and a response circuit. Specifically, the drive circuit includes a plurality of slices, where each slice receives an independent data stream and produces an independent formatted level. The response circuit includes a plurality of slices, where each slice receives an independent data stream and produces an independent strobe marker.Type: GrantFiled: May 7, 2004Date of Patent: July 27, 2010Assignee: Credence Systems CorporationInventors: Ahmed Rashid Syed, Burnell G. West
-
Patent number: 7761751Abstract: A method and system for performing diagnosing in an automatic test environment. The method begins by determining a fail condition during a test of a device under test (DUT). A diagnostic suite is determined for testing the fail condition. The diagnostic suite is generated if the diagnostic suite is not available for access.Type: GrantFiled: February 20, 2007Date of Patent: July 20, 2010Assignee: Credence Systems CorporationInventor: Burnell G. West
-
Patent number: 7454678Abstract: A system and method for processing scan data for integrated circuit testing. Scan data is divided into three groups of scan data segments: scan-in data segments, scan-out data segments and scan-mask data segments. The sequence of scan data segments in each group constitutes the operative test data in a scan stream. Each scan stream is represented by a table having a row corresponding to each scan data segment in the stream. Each row has four fields: a start address, a segment length, a start pad length and an end pad length. Scan streams consist of the bit sequence of segment data interposed by dummy data corresponding in length to the start pad and end pad lengths. Scan streams are interleaved by using the pad lengths to time the processing of scan data segments.Type: GrantFiled: August 23, 2005Date of Patent: November 18, 2008Assignee: Credence Systems CorporationInventors: Jamie S. Cullen, Burnell G. West
-
Patent number: 7336066Abstract: Testing of an electronic device is carried out by combining power and signal delivery on a single pair of wires. The power delivery is decoupled from the signal delivery, using inductors, so the device power supplied does not interfere with the test signals delivered from the device and the response signals delivered to the device. Further, simultaneous bidirectional signal paths are decoupled, using capacitors, so that the tester transceiver and the device transceiver are not damaged by the power delivered to the device on the same wires. A common fixture may be used to test a number of different types of wafers, independent of the topography, size, or power requirements of the devices on the wafers, resulting in a significant cost saving, because fixture design has become very expensive, in some cases costing more than the tester whose signals it is implemented to deliver.Type: GrantFiled: May 21, 2004Date of Patent: February 26, 2008Assignee: Credence Systems CorporationInventor: Burnell G. West
-
Patent number: 7222280Abstract: A test apparatus including a means for sending a first test pattern to a device under test (DUT), where the first test pattern is a part of a planned sequence of tests, and further including a means for evaluating the test results received from the DUT, and a method of testing are described. The test results may include anomalous data indicative of a defect in the DUT. If so, a second test pattern that is not part of the planned sequence of tests is selected. The second test pattern is selected based on a diagnosis of the anomalous data by the test apparatus.Type: GrantFiled: April 14, 2004Date of Patent: May 22, 2007Assignee: Credence Systems CorporationInventors: Burnell G. West, Rodolfo E. Garcia
-
Patent number: 7212941Abstract: A test apparatus implements a method for testing electronic devices that exhibit non-deterministic behavior. The test apparatus includes a high-speed buffer queue for storing data packets. The data packets arrive at one end of the queue and, as they exit at the other end, are compared against expect data packets stored in memory. If the data packet exiting the buffer queue corresponds to response signals generated by the device under test during a non-deterministic (e.g., idle) state, the expect data packet is not retrieved from memory and the comparison is not made.Type: GrantFiled: August 24, 2004Date of Patent: May 1, 2007Assignee: Credence Systems CorporationInventors: Angarai T. Sivaram, Burnell G. West, Howard Maassen
-
Patent number: 7171598Abstract: An apparatus for testing an integrated circuit, the apparatus including a sequence control logic unit having an output channel connectable to a device under test, and a memory to store at least two types of data sets, each data set being used by the sequence control logic unit to determine a test pattern to output on the output channel.Type: GrantFiled: May 8, 2003Date of Patent: January 30, 2007Assignee: Credence Systems CorporationInventors: Jamie S. Cullen, Burnell G. West
-
Patent number: 7143326Abstract: Testing an integrated circuit (IC) device, for example, an IC that includes an embedded memory, may involve specifying one or more test parameters including at least one of a pipeline depth data (e.g., latency delay information) and a data width data (e.g. corresponding to a data width of an embedded memory), generating a test sequence by associating test parameters with a test pattern, and applying the generated test sequence to the integrated circuit device. A test system for testing ICs having embedded memories may include multiple test patterns and multiple data structures, each data structure defining one or more test parameters including at least one of a pipeline depth and a data width, an algorithmic pattern generator, and software for controlling the algorithmic pattern generator to generate a test sequence by associating a specified data structure with a specified test pattern.Type: GrantFiled: March 19, 2002Date of Patent: November 28, 2006Assignee: Credence Systems CorporationInventors: Daniel Fan, Kris Sakaitani, Burnell G. West
-
Patent number: 7113886Abstract: A circuit and related method for distributing events in an event stream (i.e., an electronic signal having a plurality of rising edge transitions and falling edge transitions). The circuit distributes the events in a primary event stream across multiple secondary event streams in such a way that the event rate in each of the secondary event streams is lower than the event rate in the primary event stream, but the relative timing of the events in the primary event stream is maintained in each of the secondary event streams. The secondary event streams can then be provided to respective timestamp circuits, which record the times at which events occur in the secondary event streams. Since the relative timing of the events in the primary event stream is maintained in each of the secondary event streams, the multiple timestamp circuits collectively record the times at which events occur in the primary event stream. The circuit and related method can be used when debugging/testing semiconductor devices.Type: GrantFiled: January 23, 2002Date of Patent: September 26, 2006Assignee: Credence Systems CorporationInventor: Burnell G. West
-
Patent number: 7093177Abstract: Generating test signals for a device under test (DUT) involves generating a master reference signal, using a vernier technique to generate test pattern signals based on the master reference signal, generating a test clock signal that is phase-matched with and frequency similar to the test pattern signals by providing the master reference signal as input to a phase-locked loop (PLL) and controlling one or more programmable dividers in the PLL to adjust the test clock signal to be a multiple or sub-multiple of a frequency of the test pattern signals, applying the test clock signal to the clock input pin of the DUT, and applying the test pattern signals to data pins of the DUT. When the frequency of the test pattern signals is changed, the test clock signal frequency may be adjusted to calibrate to the changed frequency of the test pattern signals by re-programming the programmable dividers.Type: GrantFiled: March 19, 2002Date of Patent: August 15, 2006Assignee: Schlumberger Technologies, Inc.Inventors: Burnell G. West, Paolo Dalla Ricca
-
Patent number: 7035755Abstract: Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.Type: GrantFiled: August 16, 2002Date of Patent: April 25, 2006Assignee: Credence Systems CorporationInventors: Michael F. Jones, Robert Whyte, Jamie S. Cullen, Naveed Zaman, Yann Gazounaud, Burnell G. West, William Fritzsche
-
Patent number: 7017091Abstract: A test system formatter may include a programmable drive circuit configurable to operate in any of a plurality of drive modes, each mode corresponding to a different combination of drive signals or drive timing markers or both, and a programmable response circuit configurable to operate in any of a plurality of strobe modes, each strobe mode corresponding to a different combination of strobe signals. The formatter may also include multiple drive channels and/or multiple response channels, each channel being formed, e.g., of an event logic interface and a corresponding linear delay element. The drive channels provide signals to the drive circuit to be used to generate drive signals or drive timing markers or both. The response channels receive from one or more pin-electronics comparators response signals used to generate fail outputs. The programmable drive and response circuits are configurable to route signals through multiple channels in parallel.Type: GrantFiled: March 18, 2002Date of Patent: March 21, 2006Assignee: Credence Systems CorporationInventor: Burnell G. West
-
Patent number: 6940271Abstract: A pin electronics circuit for use in automatic test equipment may include a reconfigurable logic device in which different logic configurations may be installed to make measurements according to multiple tests to be applied to a device under test; a level generating circuit coupled to the reconfigurable logic device, and configured to generate a number of test levels and a number of reference levels; and a switching circuit, coupled to the reconfigurable logic device and the level generating circuit, configured to receive the test levels and the reference levels, and controlled by the reconfigurable logic device to selectively apply the test levels to the device under test according to a selected test and to sense levels inputted to or outputted from the device under test by comparing the reference levels generated by the level generating circuit to the levels inputted to our outputted from the device under test.Type: GrantFiled: August 9, 2002Date of Patent: September 6, 2005Assignee: NPTest, Inc.Inventor: Burnell G. West
-
Patent number: 6937006Abstract: A pin electronics circuit for use in automatic test equipment may include a reconfigurable logic device in which different logic configurations may be installed to make measurements according to multiple tests to be applied to a device under test; a level generating circuit coupled to the reconfigurable logic device, and configured to generate a number of test levels and a number of reference levels; and a switching circuit, coupled to the reconfigurable logic device and the level generating circuit, configured to receive the test levels and the reference levels, and controlled by the reconfigurable logic device to selectively apply the test levels to the device under test according to a selected test and to sense levels inputted to or outputted from the device under test by comparing the reference levels generated by the level generating circuit to the levels inputted to our outputted from the device under test.Type: GrantFiled: August 31, 2004Date of Patent: August 30, 2005Assignee: Credence Systems CorporationInventor: Burnell G. West
-
Patent number: 6928387Abstract: A circuit and method for distributing events in an event stream. A circuit for distributing events in a signal into a plurality of channels of circuitry capable of timestamping events is described. The circuit includes a first plurality of flip-flops arranged in a cascading configuration. The cascading configuration distributes a primary event stream into a first plurality of secondary event streams on each successive rising edge of the primary event stream. The circuit also includes a second plurality of flip-flops arranged in another cascading configuration for distributing the primary event stream. The primary event stream is distributed into a second plurality of secondary event streams on each successive falling edge of said primary event stream.Type: GrantFiled: May 24, 2004Date of Patent: August 9, 2005Assignee: Credence Systems CorporationInventor: Burnell G. West
-
Patent number: 6859902Abstract: A testing method and circuit used to test high-speed communication devices on Automatic Test Equipment—ATE. The method and circuit provide a solution to testing very high speed (2.5 Gbps and above) integrated circuits. The circuit fans out the data streams from the output of the Device Under Test (DUT) to multiple tester channels which under-sample the streams. The testing method and circuit also allow for the injection of jitter into to the DUT at the output of the DUT. The skipping of data bits inherent in multi-pass testing is avoided by duplicating the tester resources to achieve effective real-time capture (saving test time and improving Bit Error Rate). Moreover the circuit synchronizes different DUTs with the timing of ATE hardware independent of DUT output data. Also, a calibration method is used compensate for differing trace lengths and propagation delay characteristics of test circuit components.Type: GrantFiled: October 2, 2000Date of Patent: February 22, 2005Assignee: Credence Systems CorporationInventors: Wajih Dalal, Masashi Shimanouchi, Robert J. Glenn, Burnell G. West
-
Publication number: 20040255212Abstract: A system and method for processing scan data for integrated circuit testing. Scan data is divided into three groups of scan data segments: scan-in data segments, scan-out data segments and scan-mask data segments. The sequence of scan data segments in each group constitutes the operative test data in a scan stream. Each scan stream is represented by a table having a row corresponding to each scan data segment in the stream. Each row has four fields: a start address, a segment length, a start pad length and an end pad length. The start address is a pointer to the scan data segment in memory where the scan data segment is stored in a contiguous portion of memory. Scan data segment length is the length in bits of the segment. Start pad length is a delay value measured in number of scan clock cycles that must elapse before processing the respective segment in the scan stream.Type: ApplicationFiled: June 4, 2004Publication date: December 16, 2004Inventors: Jamie S. Cullen, Burnell G. West
-
Publication number: 20040187049Abstract: The present invention provides a method and system for testing a semiconductor device under test (DUT), such as an IC, with the help of a tester. A clock generator in the tester generates a clock signal that is sent over to the DUT on a clock signal line. Prior to an actual test, transmission and reception of data between the tester and the DUT, is synchronized with the clock signals. The invention utilizes simultaneous bi-directional signaling (SBS) for simultaneously transmitting and receiving test related data between the tester and the DUT over a single transmission line. The DUT replies with response signals corresponding to these test related data over the same transmission line. The use of SBS reduces the time required for the test, the number of pins and hence, overall cost and complexity of the testing process involved with the test.Type: ApplicationFiled: February 27, 2003Publication date: September 23, 2004Applicant: NPTEST, INC.Inventor: Burnell G. West
-
Patent number: 6748564Abstract: A system and method for processing scan data for integrated circuit testing. Scan data is divided into three groups of scan data segments: scan-in data segments, scan-out data segments and scan-mask data segments. The sequence of scan data segments in each group constitutes the operative test data in a scan stream. Each scan stream is represented by a table having a row corresponding to each scan data segment in the stream. Each row has four fields: a start address, a segment length, a start pad length and an end pad length. The start address is a pointer to the scan data segment in memory where the scan data segment is stored in a contiguous portion of memory. Scan data segment length is the length in bits of the segment. Start pad length is a delay value measured in number of scan clock cycles that must elapse before processing the respective segment in the scan stream.Type: GrantFiled: October 24, 2000Date of Patent: June 8, 2004Assignee: NPTest, LLCInventors: Jamie S. Cullen, Burnell G. West
-
Publication number: 20040039977Abstract: An apparatus for testing an integrated circuit, the apparatus including a sequence control logic unit having an output channel connectable to a device under test, and a memory to store at least two types of data sets, each data set being used by the sequence control logic unit to determine a test pattern to output on the output channel.Type: ApplicationFiled: May 8, 2003Publication date: February 26, 2004Inventors: Jamie S. Cullen, Burnell G. West