Abstract: A passenger discriminating apparatus according to the present invention includes a plurality of load sensors for measuring a load of a passenger, which is applied to a passenger seat disposed within a vehicle, and a pair of dummy sensors configured to support the load of the passenger seat and not having a load sensing function. The type of the passenger is discriminated by comparing a sum of values in which the load values measured by the plurality of load sensors, respectively, are multiplied by a load weight of the load sensors and a reference value. Accordingly, the passenger discriminating apparatus can save the prime cost, reduce its weight, and secure an equivalent or more performance.

Abstract: An apparatus for classifying passengers includes a plurality of load sensors disposed in a passenger seat of an automobile to measure a load applied to the passenger seat, the load sensors classifying the passengers by comparing a sum with a reference value, and the sum being obtained by summing the respective values, which are obtained by multiplying respective load values measured from the plurality of load sensors by weighed load values of the respective load sensors.

Abstract: Test structures for detecting defects arising from hybrid orientation technology (HOT) through detection of device leakage (gate leakage, junction leakage, and sub-threshold leakage), having at least one active region disposed in a re-grown region of a substrate: a layer of oxide; a layer of poly. Some test structures are dog-bone shaped test structure, tower shaped test structure, and inside-hole shaped. A method for detecting HOT defects involves measuring defect size and location in terms of device leakage, such as gate leakage, junction leakage, and sub-threshold leakage. HOT edge defect density and edge defect size distribution may be calculated, and the resulting defect information may be used to calibrate a defect yield model.

Abstract: A charge pump circuit in a DLL device used as a clock compensation device is disclosed. A controller for controlling current value and a driver for driving the controller are added to the existing charge pump circuit. Thus, the charge pump circuit reduces lock time and the size of output jitter so that performance of the DLL device can be improved.

Abstract: A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e., <30:1) is described. The method forms a passivation film to the extent necessary for preventing isotropic etching of the substrate, hence maintaining the required profile and the shape of the DT within the substrate. The RIE process described provides a partial DT etched into a substrate to achieve the predetermined depth. The passivation film is allowed to grow to a certain thickness still below the extent that it would close the opening of the deep trench. Alternatively, the passivation film is removed by a non-RIE etching process. The non-RIE process that removes the film can be wet etched with chemicals, such as hydrofluoric acid (buffered or non buffered) or, alternatively, using vapor phase and/or non-ionized chemicals, such as anhydrous hydrofluoric acid.

Abstract: A method for forming an isolation region within a semiconductor device is disclosed. A trench is first formed in a predefined isolation region of a semiconductor substrate. An oxidation blocking material is injected into the inside walls of the trench before growing a field oxide film inside the trench. Accordingly, the present invention can simplify the fabrication of isolation regions within a semiconductor device by directly implanting the oxidation blocking material at a predetermined angle into the inside walls of the trench which constitutes the isolation region. In the present invention, unlike conventional fabrication processes using spacers to prevent penetration of a field oxide film into the surface of semiconductor non-isolation regions, the need for spacers is obviated.

Abstract: In an element isolation method of a semiconductor device which can form an element isolation region having a flat surface without regard to the width of the element isolation region, and whose width is below the resolution limit, an insulating film having an aperture in order to define the element isolation region is formed on the semiconductor wafer, wherein an oxidizable material layer is deposited and then first spacers are formed on the sidewalls of the aperture. Then, a thermal oxide film is formed over the entire semiconductor wafer, excluding a first-spacer-formed region, and the first spacer is removed. The wafer surface is exposed to the lower part of the removed first spacer region, and then the portion of the semiconductor wafer below the exposed region is etched to thereby form a trench. After that, an element isolation region is formed by filling up the trench and removing the insulating film around tile trench.

Abstract: An isolation method in a semiconductor device which includes the steps of growing a pad oxide layer on a semiconductor substrate, depositing a polysilicon layer and a first silicon nitride layer on the pad oxide layer, removing and patterning the first silicon nitride layer to define an active region and a field region, depositing a second silicon nitride layer and a thick oxide layer, forming oxide spacers and nitride spacers, ion-implanting impurities, removing the oxide spacers, growing a field oxide layer, and sequentially removing the first silicon nitride layer, the nitride spacers, the polysilicon layer, and the pad oxide layer. This method minimizes the bird's beaks regions and increases the effective isolation distance of the device.