Abstract: A display substrate includes a substrate, a pixel part, a pad part and a sacrificial electrode. The substrate includes a display area and a peripheral area. The pixel part is on the display area and includes a switching element, and a pixel electrode electrically connected to the switching element. The pad part is on the peripheral area and contacts a terminal of an external device. The pad part includes a pad electrode a contact electrode. The pad electrode includes a first metal layer, and a second metal layer on the first metal layer, and the contact electrode contacts the second metal layer. The sacrificial electrode is spaced apart from the pad electrode and contacts the contact electrode. An exposed portion of the sacrificial electrode is exposed to an external side of the display substrate.

Abstract: A display substrate includes a substrate, a pixel part, a pad part and a sacrificial electrode. The substrate includes a display area and a peripheral area. The pixel part is on the display area and includes a switching element, and a pixel electrode electrically connected to the switching element. The pad part is on the peripheral area and contacts a terminal of an external device. The pad part includes a pad electrode a contact electrode. The pad electrode includes a first metal layer, and a second metal layer on the first metal layer, and the contact electrode contacts the second metal layer. The sacrificial electrode is spaced apart from the pad electrode and contacts the contact electrode. An exposed portion of the sacrificial electrode is exposed to an external side of the display substrate.

Abstract: A method of forming a semiconductor device can include forming a trench in a semiconductor substrate to define an active region. The trench is filled with a first device isolation layer. A portion of the first device isolation layer is etched to recess a top surface of the first device isolation layer below an adjacent top surface of the active region of the semiconductor substrate and to partially expose a sidewall of the active region. The exposed sidewall of the active region is epitaxially grown to form an extension portion of the active region that extends partially across the top surface of the first device isolation layer in the trench. A second device isolation layer is formed on the recessed first device isolation layer in the trench. The second device isolation layer is etched to expose a top surface of the extension portion of the active region and leave a portion of the second device isolation layer between extension portions of active regions on opposite sides of the trench.

Abstract: A method of forming a semiconductor device can include forming a trench in a semiconductor substrate to define an active region. The trench is filled with a first device isolation layer. A portion of the first device isolation layer is etched to recess a top surface of the first device isolation layer below an adjacent top surface of the active region of the semiconductor substrate and to partially expose a sidewall of the active region. The exposed sidewall of the active region is epitaxially grown to form an extension portion of the active region that extends partially across the top surface of the first device isolation layer in the trench. A second device isolation layer is formed on the recessed first device isolation layer in the trench. The second device isolation layer is etched to expose a top surface of the extension portion of the active region and leave a portion of the second device isolation layer between extension portions of active regions on opposite sides of the trench.

Abstract: A method of forming a capacitor can include etching a metal-nitride layer in an environment comprising fluorine and oxygen to form a capacitor electrode.

Abstract: Methods of forming capacitor structures may include forming an insulating layer on a substrate, forming a first capacitor electrode on the insulating layer, forming a capacitor dielectric layer on portions of the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric layer such that the capacitor dielectric layer is between the first and second capacitor electrodes. More particularly, the first capacitor electrode may define a cavity therein wherein the cavity has a first portion parallel with respect to the substrate and a second portion perpendicular with respect to the substrate. Related structures are also discussed.

Abstract: Methods of forming field effect transistors include the steps of forming a first electrically insulating layer on a semiconductor substrate having a plurality of trench isolation regions therein that define an active region therebetween. The first electrically insulating layer is then patterned to define a first plurality of openings therein that extend opposite the active region. A trench mask having a second plurality of openings therein is then formed by filling the first plurality of openings with electrically insulating plugs and then etching the patterned first electrically insulating layer using the electrically insulating plugs as an etching mask. A plurality of trenches are then formed in the active region by etching the semiconductor substrate using the trench mask as an etching mask. A plurality of insulated gate electrodes are then formed that extend into the plurality of trenches.

Abstract: Methods for etching a metal layer and a metallization method of a semiconductor device using an etching gas that includes Cl2 and N2 are provided. A mask layer is formed on the metal layer, the etching gas is supplied to the metal layer, and the metal layer is etched by the etching gas using the mask layer as an etch mask. The metal layer may be formed of aluminum or an aluminum alloy. Cl2 and N2 may be mixed at a ratio of 1:1 to 1:10. The etching gas may also include additional gases such as inactive gases or gases that include the elements H, O, F, He, or C. In addition, N2 may be supplied at a flow rate of from 45–65% of the total flow rate of the etching gas, which results in a reduction in the occurrence of micro-loading and cone-shaped defects in semiconductor devices.

Abstract: A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided.

Abstract: A method of forming a capacitor for a semiconductor device is disclosed. According to the method, a silicon germanium layer and an oxide layer are used as mold layers for forming a storage electrode. The oxide layer and the silicon germanium layer are anisotropically etched to form an opening and then the silicon germanium layer is further isotropically etched to form a recessed portion of the opening, such that the recessed portion of the opening formed in the silicon germanium layer is wider than at least some portion of the opening through the oxide layer. Thus, the mold layers are used to form a storage electrode having a lower portion which is wider than an upper portion thereof.

Abstract: A method of forming self-aligned contact holes exposing source/drain regions in a semiconductor substrate using only etch mask layers is provided. In the method, sacrificial spacers are formed of a material having an excellent etching selectivity to the etch mask layers at sidewalls of gate electrodes in a cell area. Also, an interlevel dielectric layer is formed of a material having an excellent etching selectivity to the etch mask layers. The sacrificial spacers are removed when forming the self-aligned contact holes. Dielectric spacers are formed of a material having a low dielectric constant, without considering its etching selectivity to the interlevel dielectric layer. Thus, a reduction in the operational speed of a semiconductor device having transistors can be prevented.

Abstract: An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.

Abstract: A method of forming a capacitor can include etching a metal-nitride layer in an environment comprising fluorine and oxygen to form a capacitor electrode.

Abstract: A semiconductor memory device includes a bit line stack and a storage node contact hole which are aligned at bit line spacers formed at both side walls of the bit line stack and exposes a pad. The semiconductor memory device includes a multi-layered storage node contact plug in which a first storage node contact plug and a second storage node contact plug are sequentially formed. The first storage node contact plug is formed of titanium nitride and the second storage node contact plug is formed of polysilicon. An ohmic layer may be formed on the pad and under the first storage node contact plug. A barrier metal layer, which acts as a third storage node contact plug, may be formed on the second storage node contact plug.

Abstract: Methods of forming field effect transistors include the steps of forming a first electrically insulating layer on a semiconductor substrate having a plurality of trench isolation regions therein that define an active region therebetween. The first electrically insulating layer is then patterned to define a first plurality of openings therein that extend opposite the active region. A trench mask having a second plurality of openings therein is then formed by filling the first plurality of openings with electrically insulating plugs and then etching the patterned first electrically insulating layer using the electrically insulating plugs as an etching mask. A plurality of trenches are then formed in the active region by etching the semiconductor substrate using the trench mask as an etching mask. A plurality of insulated gate electrodes are then formed that extend into the plurality of trenches.

Abstract: A method of forming a capacitor for a semiconductor device is disclosed. According to the method, a silicon germanium layer and an oxide layer are used as mold layers for forming a storage electrode. The oxide layer and the silicon germanium layer are anisotropically etched to form an opening and then the silicon germanium layer is further isotropically etched to form a recessed portion of the opening, such that the recessed portion of the opening formed in the silicon germanium layer is wider than at least some portion of the opening through the oxide layer. Thus, the mold layers are used to form a storage electrode having a lower portion which is wider than an upper portion thereof.

Abstract: The present invention provides methods of fabricating integrated circuit devices that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

Abstract: A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided.

Abstract: Methods of forming capacitor structures may include forming an insulating layer on a substrate, forming a first capacitor electrode on the insulating layer, forming a capacitor dielectric layer on portions of the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric layer such that the capacitor dielectric layer is between the first and second capacitor electrodes. More particularly, the first capacitor electrode may define a cavity therein wherein the cavity has a first portion parallel with respect to the substrate and a second portion perpendicular with respect to the substrate. Related structures are also discussed.

Abstract: A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided.