Abstract: The present invention provides methods of fabricating integrated circuit devices that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

Abstract: An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.

Abstract: The present invention provides methods of fabricating integrated circuit devices that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

Abstract: A semiconductor memory device includes a bit line stack and a storage node contact hole which are aligned at bit line spacers formed at both side walls of the bit line stack and exposes a pad. The semiconductor memory device includes a multi-layered storage node contact plug in which a first storage node contact plug and a second storage node contact plug are sequentially formed. The first storage node contact plug is formed of titanium nitride and the second storage node contact plug is formed of polysilicon. An ohmic layer may be formed on the pad and under the first storage node contact plug. A barrier metal layer, which acts as a third storage node contact plug, may be formed on the second storage node contact plug.

Abstract: Methods for etching a metal layer and a metallization method of a semiconductor device using an etching gas that includes Cl2 and N2 are provided. A mask layer is formed on the metal layer, the etching gas is supplied to the metal layer, and the metal layer is etched by the etching gas using the mask layer as an etch mask. The metal layer may be formed of aluminum or an aluminum alloy. Cl2 and N2 may be mixed at a ratio of 1:1 to 1:10. The etching gas may also include additional gases such as inactive gases or gases that include the elements H, O, F, He, or C. In addition, N2 may be supplied at a flow rate of from 45-65% of the total flow rate of the etching gas, which results in a reduction in the occurrence of micro-loading and cone-shaped defects in semiconductor devices.

Abstract: An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.

Abstract: There is provided a method of fabricating a semiconductor memory device having a self-aligned contact, including the steps of forming a plurality of gate electrodes by interposing a gate insulating layer on an active region of a semiconductor substrate in a predetermined direction at constant intervals, forming a first insulating layer on the resultant structure having the gate electrodes and then forming one or more of each of first and second openings which partially open an active region of the semiconductor substrate, forming first and second pad layers by filling the first and second openings with a conductive material, forming a first interlayer dielectric film on the first insulating layer having the first and second pad layers and forming a third opening which opens the surface of the first pad layer, forming a plurality of bit lines in a direction orthogonal to the gate electrodes on the first interlayer dielectric film while filling the third opening, depositing an insulating layer on the resultant

Abstract: The present invention provide integrated circuit devices and methods of fabricating the same that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

Abstract: A semiconductor memory device includes a bit line stack and a storage node contact hole which are aligned at bit line spacers formed at both side walls of the bit line stack and exposes a pad. The semiconductor memory device includes a multi-layered storage node contact plug in which a first storage node contact plug and a second storage node contact plug are sequentially formed. The first storage node contact plug is formed of titanium nitride and the second storage node contact plug is formed of polysilicon. An ohmic layer may be formed on the pad and under the first storage node contact plug. A barrier metal layer, which acts as a third storage node contact plug, may be formed on the second storage node contact plug.

Abstract: A method of forming self-aligned contact holes exposing source/drain regions in a semiconductor substrate using only etch mask layers is provided. In the method, sacrificial spacers are formed of a material having an excellent etching selectivity to the etch mask layers at sidewalls of gate electrodes in a cell area. Also, an interlevel dielectric layer is formed of a material having an excellent etching selectivity to the etch mask layers. The sacrificial spacers are removed when forming the self-aligned contact holes. Dielectric spacers are formed of a material having a low dielectric constant, without considering its etching selectivity to the interlevel dielectric layer. Thus, a reduction in the operational speed of a semiconductor device having transistors can be prevented.

Abstract: A method of forming self-aligned contact holes exposing source/drain regions in a semiconductor substrate using only etch mask layers is provided. In the method, sacrificial spacers are formed of a material having an excellent etching selectivity to the etch mask layers at sidewalls of gate electrodes in a cell area. Also, an interlevel dielectric layer is formed of a material having an excellent etching selectivity to the etch mask layers. The sacrificial spacers are removed when forming the self-aligned contact holes. Dielectric spacers are formed of a material having a low dielectric constant, without considering its etching selectivity to the interlevel dielectric layer. Thus, a reduction in the operational speed of a semiconductor device having transistors can be prevented.

Abstract: There is provided a method of fabricating a semiconductor memory device having a self-aligned contact, including the steps of forming a plurality of gate electrodes by interposing a gate insulating layer on an active region of a semiconductor substrate in a predetermined direction at constant intervals, forming a first insulating layer on the resultant structure having the gate electrodes and then forming one or more of each of first and second openings which partially open an active region of the semiconductor substrate, forming first and second pad layers by filling the first and second openings with a conductive material, forming a first interlayer dielectric film on the first insulating layer having the first and second pad layers and forming a third opening which opens the surface of the first pad layer, forming a plurality of bit lines in a direction orthogonal to the gate electrodes on the first interlayer dielectric film while filling the third opening, depositing an insulating layer on the resultant

Abstract: Methods are provided for conductively contacting an integrated circuit, including a plurality of spaced apart lines thereon, using a dummy dielectric layer. A dummy dielectric layer is formed between first selected ones of the spaced apart lines. An interdielectric layer is formed between second selected ones of the spaced apart lines that are different from the first selected ones of the lines. The interdielectric layer has a lower etch rate than the dummy dielectric layer with respect to a predetermined etchant. The dummy dielectric layer is etched with the predetermined etchant, to remove at least some of the dummy dielectric layer between the first selected ones of the spaced apart lines. A conductive layer is formed between the first selected ones of the spaced apart lines from which at least some of the dummy dielectric layer has been removed, to electrically contact the integrated circuit between the first selected ones of the spaced apart lines.

Abstract: A method of manufacturing a self-aligned contact hole. Gate patterns are formed on a semiconductor substrate with an interposing gate insulating layer, and a first insulating pattern for filling a gap between the gate patterns is provided. A portion of the first insulating pattern is etched by self-aligned contact etching to form a first contact hole. A spacer is formed on a side wall of the first contact hole, and a first plug layer of conductive silicon fills the first contact hole. Partial etchback is performed to etch the first plug and gate pattern to a predetermined thickness, such that the top portion of the spacer projects higher than the surface of the first plug and gate pattern. A second plug layer of conductive silicon fills a gap between the projected spacers, and a thickness of the second plug layer at a portion filling the gap between the spacers is greater than that at a portion deposited on the gate pattern.

Abstract: A method of forming self-aligned contact holes exposing source/drain regions in a semiconductor substrate using only etch mask layers is provided. In the method, sacrificial spacers are formed of a material having an excellent etching selectivity to the etch mask layers at sidewalls of gate electrodes in a cell area. Also, an interlevel dielectric layer is formed of a material having an excellent etching selectivity to the etch mask layers. The sacrificial spacers are removed when forming the self-aligned contact holes. Dielectric spacers are formed of a material having a low dielectric constant, without considering its etching selectivity to the interlevel dielectric layer. Thus, a reduction in the operational speed of a semiconductor device having transistors can be prevented.

Abstract: A method for forming a conductive contact of a semiconductor device is provided. According to one aspect of the present invention, a dummy dielectric layer pattern having a dummy opening and an interdielectric layer pattern having a lower etch-rate than that of the dummy dielectric layer, for filling the dummy opening are formed on a semiconductor substrate. The dummy dielectric layer pattern using the interdielectric layer pattern as an etching mask is selectively removed, and a contact opening for exposing the semiconductor substrate of a portion in which the dummy dielectric layer pattern is located.

Abstract: The present invention provide integrated circuit devices and methods of fabricating the same that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

Abstract: A semiconductor memory device includes a bit line stack and a storage node contact hole which are aligned at bit line spacers formed at both side walls of the bit line stack and exposes a pad. The semiconductor memory device includes a multi-layered storage node contact plug in which a first storage node contact plug and a second storage node contact plug are sequentially formed. The first storage node contact plug is formed of titanium nitride and the second storage node contact plug is formed of polysilicon. An ohmic layer may be formed on the pad and under the first storage node contact plug. A barrier metal layer, which acts as a third storage node contact plug, may be formed on the second storage node contact plug.

Abstract: An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.

Abstract: There is provided a method of fabricating a semiconductor memory device having a self-aligned contact, including the steps of forming a plurality of gate electrodes by interposing a gate insulating layer on an active region of a semiconductor substrate in a predetermined direction at constant intervals, forming a first insulating layer on the resultant structure having the gate electrodes and then forming one or more of each of first and second openings which partially open an active region of the semiconductor substrate, forming first and second pad layers by filling the first and second openings with a conductive material, forming a first interlayer dielectric film on the first insulating layer having the first and second pad layers and forming a third opening which opens the surface of the first pad layer, forming a plurality of bit lines in a direction orthogonal to the gate electrodes on the first interlayer dielectric film while filling the third opening, depositing an insulating layer on the resultant