Abstract: A method for forming a conductive contact of a semiconductor device is provided. According to one aspect of the present invention, a dummy dielectric layer pattern having a dummy opening and an interdielectric layer pattern having a lower etch-rate than that of the dummy dielectric layer, for filling the dummy opening are formed on a semiconductor substrate. The dummy dielectric layer pattern using the interdielectric layer pattern as an etching mask is selectively removed, and a contact opening for exposing the semiconductor substrate of a portion in which the dummy dielectric layer pattern is located.

Abstract: A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided.

Abstract: A semiconductor device having a self-aligned contact and a method for fabricating the same are provided. The semiconductor device includes a plurality of conductive patterns formed to be adjacent to one another by sequentially stacking and patterning a first conductive layer and a mask layer on a particular underlying layer. A first insulation layer fills a gap between adjacent conductive layer patterns such that the upper portion of each conductive layer pattern is exposed. A second insulation layer having a spacer shape is formed on the sides of each conductive layer pattern exposed above the first insulation layer. A second conductive layer fills a contact hole which is self-aligned with respect to the second insulation layers between adjacent conductive layer patterns and passes through the first insulation layer.

Abstract: A method of manufacturing a self-aligned contact hole. Gate patterns are formed on a semiconductor substrate with an interposing gate insulating layer, and a first insulating pattern for filling a gap between the gate patterns is provided. A portion of the first insulating pattern is etched by self-aligned contact etching to form a first contact hole. A spacer is formed on a side wall of the first contact hole, and a first plug layer of conductive silicon fills the first contact hole. Partial etchback is performed to etch the first plug and gate pattern to a predetermined thickness, such that the top portion of the spacer projects higher than the surface of the first plug and gate pattern. A second plug layer of conductive silicon fills a gap between the projected spacers, and a thickness of the second plug layer at a portion filling the gap between the spacers is greater than that at a portion deposited on the gate pattern.

Abstract: A method for forming a patterned platinum layer on a microelectronic substrate includes the steps of forming a platinum layer on the microelectronic substrate, and forming a mask layer on the platinum layer. In particular, the mask layer defines exposed portions of the platinum layer, and the mask layer comprises a mask material including titanium. The exposed portions of the platinum layer are then selectively removed to form the patterned platinum layer. Related structures are also disclosed.

Abstract: A method of etching a platinum group metal film uses a gas mixture containing argon (Ar), oxygen (O2) and halogen gases and a method of forming a lower electrode of a capacitor uses the etching method. The gas mixture contains O2, Ar, and a third component, preferably a halogen, e.g., chlorine (Cl2) or hydrogen bromide (HBr). In the method of forming a lower electrode, a conductive film containing a metal belonging to a platinum (Pt) group is formed on a semiconductor substrate, a hard mask partially exposing the conductive film is then formed on the conductive film. Then, the exposed conductive film is dry-etched using the hard mask as an etching mask and a three-component gas mixture containing argon (Ar) and oxygen (O2), to form a conductive film pattern beneath the hard mask, and the hard mask is then removed.

Abstract: A method of etching a platinum (Pt) layer of a semiconductor device includes the steps of forming a platinum layer on a semiconductor substrate, and forming a mask layer on the platinum layer. A photoresist pattern is formed on the mask layer and a mask pattern is formed by plasma-etching using the photoresist pattern as a mask. A platinum pattern is formed by plasma-etching using the photoresist pattern and the mask pattern as a mask. A platinum etching by-product is formed on the sidewalls of the photoresist pattern. The platinum layer is plasma-etched using Ar, Ar/Cl.sub.2 or Ar/HBr gas. The photoresist pattern is removed and then the platinum etching by-product and the mask pattern are removed by plasma etching. The platinum etching by-product is plasma-etched using Cl.sub.2 /O.sub.2 or HBr/O.sub.2 gas. The platinum pattern may be formed in the same etch chamber through multiple steps, and the platinum layer is etched using Ar, Ar/Cl.sub.

Abstract: A method for etching a platinum (Pt) layer of a semiconductor device is provided which improves the etching slope of a sidewall of the platinum layer used as a storage node of the semiconductor device. The semiconductor device consists of a semiconductor substrate including a bottom layer on which various other layers are formed. Specifically, according to this invention, a Pt layer is formed on a bottom layer of a semiconductor substrate. An adhesive layer is then formed on the Pt layer while a mask layer is formed on the adhesive layer. After formation of the various layers, the mask layer and adhesive layer are patterned using an etching process to form a mask pattern and an adhesive layer mask pattern, respectively. The semiconductor substrate is then heated and an etching process is performned on the Pt layer using the mask pattern and the adhesive layer mask pattern to form etching slope sidewalls of the Pt layer having etching slopes close to vertical.

Abstract: Methods of forming field effect transistors include the steps of forming a composite of layers including an amorphous silicon layer (a--Si), a silicon dioxide layer thereon and a silicon nitride layer on the silicon dioxide layer. A polycrystalline silicon conductive layer is then formed on the silicon nitride layer by depositing and patterning polycrystalline silicon. The polycrystalline silicon conductive layer is then oxidized using thermal oxidation techniques to form an oxide outerlayer. During this step, a portion of the polycrystalline silicon conductive layer will be consumed to define a gate electrode. Dopants of first conductivity type are then implanted into a top surface of the silicon nitride layer, using the oxide outerlayer and the gate electrode as a mask, to form relatively lightly doped preliminary source and drain regions in the amorphous silicon layer. The oxide outerlayer is then removed preferably using a buffered oxide etchant (BOE) solution which does not etch silicon nitride.