Patents by Inventor Byong Jin Kim

Byong Jin Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12334420
    Abstract: An electronic device includes a substrate with a conductive structure and a substrate encapsulant. The conductive structure has a lead with a lead via and a lead protrusion. The lead via can include via lateral sides defined by first concave portions and the lead protrusion can include protrusion lateral sides defined by second concave portions. The substrate encapsulant covers the first concave portions at a first side of the substrate but not the second concave portions so that the lead protrusion protrudes from the substrate encapsulant at a second side of the substrate. An electronic component can be adjacent to the first side of the substrate and electrically coupled to the conductive structure. A body encapsulant encapsulates portions of the electronic component and the substrate. The lead can further include a lead trace at the second side of the substrate.
    Type: Grant
    Filed: December 15, 2023
    Date of Patent: June 17, 2025
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Hyeong Il Jeon, Gi Jeong Kim, Yong Ho Son, Byong Jin Kim, Jae Min Bae, Seung Woo Lee
  • Publication number: 20250192093
    Abstract: In one example, a semiconductor device comprises an electronic component comprising a component face side, a component base side, a component lateral side connecting the component face side to the component base side, and a component port adjacent to the component face side, wherein the component port comprises a component port face. A clip structure comprises a first clip pad, a second clip pad, a first clip leg connecting the first clip pad to the second clip pad, and a first clip face. An encapsulant covers portions of the electronic component and the clip structure. The encapsulant comprises an encapsulant face, the first clip pad is coupled to the electronic component, and the component port face and the first clip face are exposed from the encapsulant face. Other examples and related methods are also disclosed herein.
    Type: Application
    Filed: February 19, 2025
    Publication date: June 12, 2025
    Applicant: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Ji Yeon RYU, Jae Beom SHIM, Tai Yong LEE, Byong Jin KIM
  • Publication number: 20250149429
    Abstract: In one example, an electronic device comprises a substrate defining an opening between interior sidewalls. An electronic component is disposed in the opening. A lid is disposed beneath the substrate and a first side of the electronic component, and the lid is thermally coupled to the electronic component. Component interconnects can be coupled to a second side of the electronic component opposite the first side. An antenna structure is disposed over the electronic component and electronically coupled to electronic component through the component interconnects. Other examples and related methods are also disclosed herein.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 8, 2025
    Applicant: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Kyoung Yeon Lee, Byong Jin Kim, Sang Hyeon Lee
  • Patent number: 12261145
    Abstract: In one example, a semiconductor device comprises an electronic component comprising a component face side, a component base side, a component lateral side connecting the component face side to the component base side, and a component port adjacent to the component face side, wherein the component port comprises a component port face. A clip structure comprises a first clip pad, a second clip pad, a first clip leg connecting the first clip pad to the second clip pad, and a first clip face. An encapsulant covers portions of the electronic component and the clip structure. The encapsulant comprises an encapsulant face, the first clip pad is coupled to the electronic component, and the component port face and the first clip face are exposed from the encapsulant face. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: March 25, 2025
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Ji Yeon Ryu, Jae Beom Shim, Tai Yong Lee, Byong Jin Kim
  • Publication number: 20250022857
    Abstract: In one example, an electronic device can include a first redistribution structure. A first electronic component can be disposed on a first side of the first redistribution structure. A first passive component can be on a second side of the first redistribution structure with the first redistribution structure between the first passive component and the first electronic component. A first internal interconnect can be adjacent a lateral side of the first redistribution structure and coupled to the first redistribution structure. A second internal interconnect can be adjacent a lateral side of the first passive component and coupled to the first redistribution structure. An antenna substrate can be disposed over a first side of the first electronic component. A second redistribution structure can be disposed over a second side of the first electronic component. Other examples and related methods are also disclosed herein.
    Type: Application
    Filed: July 10, 2023
    Publication date: January 16, 2025
    Applicant: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Kyoung Yeon Lee, Byong Jin Kim, Ji Yeon Ryu
  • Publication number: 20240404902
    Abstract: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.
    Type: Application
    Filed: August 12, 2024
    Publication date: December 5, 2024
    Applicant: Amkor Technology Singapore Holding Pte. Ltd
    Inventors: Won Bae BANG, Byong Jin KIM, Gi Jeong KIM, Jae Doo KWON, Hyung Il JEON
  • Publication number: 20240387333
    Abstract: A packaged electronic device includes a molded substrate with a conductive structure having an edge lead with an edge lead outward side and an edge lead inward side; an inner lead having an inner lead outward side and an inner lead inward side; and a substrate encapsulant. An electronic component is connected to the edge lead and the inner lead. A body encapsulant covers the electronic component and portions of the conductive structure. An upper portion of the edge lead outward side is exposed from one side of the body encapsulant. A conductive cover is over a top side and sides of the body encapsulant and outer sides of the substrate encapsulant. The conductive cover contacts the upper portion of the edge lead outward side.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Applicant: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Gi Jeong KIM, Hyeong Il JEON, Byong Jin KIM, Junichiro ABE
  • Publication number: 20240332781
    Abstract: A semiconductor device includes a substrate including a conductive transceiver pattern proximate to the substrate top side. An antenna structure includes an antenna dielectric structure coupled to the substrate top side, an antenna conductive structure having an antenna element, and a cavity below the antenna element. The antenna element overlies the conductive transceiver pattern. The cavity includes a cavity ceiling, a cavity base, and a cavity sidewall. Either a bottom surface of the antenna element defines the cavity ceiling and a perimeter portion of the antenna element is fixed to the antenna dielectric structure, or the antenna dielectric structure includes a body portion having a bottom surface that defines the cavity ceiling and the antenna element is vertically spaced apart from the bottom surface of the body portion. A semiconductor component is coupled to the substrate bottom side and the transceiver pattern.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Applicant: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Corey REICHMAN, Kyoung Yeon LEE, Se Man OH, Byong Jin KIM
  • Publication number: 20240332159
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.
    Type: Application
    Filed: June 4, 2024
    Publication date: October 3, 2024
    Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
  • Patent number: 12062833
    Abstract: A method for forming packaged electronic device structure includes providing a conductive leadframe. The leadframe can include a die pad and a plurality of conductive leads. The method can include coupling an electronic device to the plurality of conductive leads. The method can include providing an antenna structure, which can include a conductive pillar structure and an elongated conductive beam structure. The method can include providing a package body encapsulating the electronic device, at least portions of each conductive lead, and at least portions of the die pad. In an example, the conductive pillar structure can extend from the first package body surface to the second package body surface, the elongated conductive beam structure can be disposed adjoining the first package body surface and can be electrically connected to the conductive pillar structure, and a portion of the elongated conductive beam structure can be exposed outside of the package body.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: August 13, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Marc Alan Mangrum, Hyung Jun Cho, Byong Jin Kim, Gi Jeong Kim, Jae Min Bae, Seung Mo Kim, Young Ju Lee
  • Patent number: 12062588
    Abstract: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: August 13, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Won Bae Bang, Byong Jin Kim, Gi Jeong Kim, Jae Doo Kwon, Hyung Il Jeon
  • Patent number: 12057378
    Abstract: In one example, a packaged electronic device includes a molded substrate. The molded substrate includes a conductive structure having an edge lead with an edge lead outward side and an edge lead inward side opposite to the edge lead outward side, and an inner lead having an inner lead outward side and an inner lead inward side opposite to the inner lead outward side. The molded substrate includes a substrate encapsulant covering a lower portion of the edge lead inward side, a lower portion of the inner lead inward side, and a lower portion of the inner lead outward side. An upper portion of the edge lead outward side and an upper portion of the inner lead outward side are exposed from the substrate encapsulant. An electronic component is connected to the edge lead and the inner lead. A body encapsulant covers the electronic component and portions of the conductive structure.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: August 6, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Gi Jeong Kim, Hyeong Il Jeon, Byong Jin Kim, Junichiro Abe
  • Publication number: 20240258225
    Abstract: An electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns, wherein the land bottom surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer. In one embodiment, a package body encapsulates the top surface of the insulating material and the electronic device, wherein the land bottom surfaces are exposed to the outside of the package body.
    Type: Application
    Filed: April 10, 2024
    Publication date: August 1, 2024
    Applicant: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Won Bae BANG, Byong Jin KIM, Gi Jeong KIM, Ji Young CHUNG
  • Patent number: 12046798
    Abstract: In one example, a semiconductor device, includes a substrate having a substrate top side, a substrate bottom side, a substrate dielectric structure, and a substrate conductive structure. The substrate conductive structure includes a transceiver pattern proximate to a substrate top side. An antenna structure includes an antenna dielectric structure coupled to the substrate top side, an antenna conductive structure having an antenna element, and a cavity below the antenna element. The antenna element overlies the transceiver pattern. The cavity includes a cavity ceiling, a cavity base, and a cavity sidewall between the cavity ceiling and the cavity base.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: July 23, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Corey Reichman, Kyoung Yeon Lee, Se Man Oh, Byong Jin Kim
  • Publication number: 20240234232
    Abstract: In one example, an electronic device comprises a base, a substrate over the base and comprising a top side, a bottom side, and a conductive structure, wherein the substrate further comprises a channel opening and an aperture, and wherein the bottom side of the substrate is oriented toward the base, an electronic component over the top side of the substrate and over the aperture, wherein the electronic component is coupled with the conductive structure, and a funnel over the top side of the substrate and comprising a funnel opening. A top side of the electronic component is exposed through the funnel opening. Other examples and related methods are also disclosed herein.
    Type: Application
    Filed: October 21, 2022
    Publication date: July 11, 2024
    Applicant: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Hyeon Gyu Lee, Byong Jin Kim, Kyoung Yeon Lee
  • Publication number: 20240194572
    Abstract: A semiconductor package structure includes a substrate comprising a land structure. The land structure includes a first land section having a first height in a cross-sectional view and a second land section having a second height in the cross-sectional view that is different than the first height. A mold encapsulant is disposed adjacent a lateral portion of the first land section and is disposed below a bottom portion of the second land section. A semiconductor die is attached to the substrate, and includes a first major surface, a second major surface opposing the first major surface, and an outer perimeter. The semiconductor die further includes a bonding structure disposed adjacent the first major surface, which is coupled to the second land section such that the first land section is disposed outside the perimeter of the semiconductor die A mold member encapsulates at least portions of the semiconductor die.
    Type: Application
    Filed: February 17, 2024
    Publication date: June 13, 2024
    Applicant: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Kyoung Yeon LEE, Byong Jin KIM, Jae Min BAE, Hyung Il JEON, Gi Jeong KIM, Ji Young CHUNG
  • Patent number: 12009289
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: June 11, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
  • Publication number: 20240136242
    Abstract: In one example, an electronic device comprises a base, a substrate over the base and comprising a top side, a bottom side, and a conductive structure, wherein the substrate further comprises a channel opening and an aperture, and wherein the bottom side of the substrate is oriented toward the base, an electronic component over the top side of the substrate and over the aperture, wherein the electronic component is coupled with the conductive structure, and a funnel over the top side of the substrate and comprising a funnel opening. A top side of the electronic component is exposed through the funnel opening. Other examples and related methods are also disclosed herein.
    Type: Application
    Filed: October 20, 2022
    Publication date: April 25, 2024
    Applicant: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Hyeon Gyu Lee, Byong Jin Kim, Kyoung Yeon Lee
  • Patent number: 11961794
    Abstract: An electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns, wherein the land bottom surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer. In one embodiment, a package body encapsulates the top surface of the insulating material and the electronic device, wherein the land bottom surfaces are exposed to the outside of the package body.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: April 16, 2024
    Assignee: Amikor Technology Singapore Holding Pte. Ltd.
    Inventors: Won Bae Bang, Byong Jin Kim, Gi Jeong Kim, Ji Young Chung
  • Publication number: 20240120262
    Abstract: An electronic device includes a substrate with a conductive structure and a substrate encapsulant. The conductive structure has a lead with a lead via and a lead protrusion. The lead via can include via lateral sides defined by first concave portions and the lead protrusion can include protrusion lateral sides defined by second concave portions. The substrate encapsulant covers the first concave portions at a first side of the substrate but not the second concave portions so that the lead protrusion protrudes from the substrate encapsulant at a second side of the substrate. An electronic component can be adjacent to the first side of the substrate and electrically coupled to the conductive structure. A body encapsulant encapsulates portions of the electronic component and the substrate. The lead can further include a lead trace at the second side of the substrate.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 11, 2024
    Applicant: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Hyeong Il JEON, Gi Jeong KIM, Yong Ho SON, Byong Jin KIM, Jae Min BAE, Seung Woo LEE