Patents by Inventor Byoung Gue Min
Byoung Gue Min has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150380482Abstract: Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.Type: ApplicationFiled: March 13, 2015Publication date: December 31, 2015Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Ho Kyun AHN, Hae Cheon KIM, Jong Won LIM, Dong Min KANG, Yong Hwan KWON, SEONG IL KIM, Zin Sig KIM, Eun Soo NAM, Byoung Gue MIN, Hyung Sup YOON, Kyung Ho LEE, Jong Min LEE, Kyu Jun CHO
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Patent number: 9224830Abstract: A field effect transistor is provided. The transistor may include a source electrode and a drain electrode provided spaced apart from each other on a substrate and a ‘+’-shaped gate electrode provided on a portion of the substrate located between the source and drain electrodes.Type: GrantFiled: June 11, 2013Date of Patent: December 29, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seong-Il Kim, Jong-Won Lim, Dong Min Kang, Sang-Heung Lee, Hyung Sup Yoon, Chull Won Ju, Byoung-Gue Min, Jongmin Lee, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 9166011Abstract: Disclosed are a semiconductor device having a stable gate structure, and a manufacturing method thereof, in which a gate structure is stabilized by additionally including a plurality of gate feet under a gate head in a width direction of the gate head so as to serve as supporters in a gate structure including a fine gate foot having a length of 0.2 ?m or smaller, and the gate head having a predetermined size. Accordingly, it is possible to prevent the gate electrode of the semiconductor device from collapsing, and improve reliability of the semiconductor device during or after the process of the semiconductor device.Type: GrantFiled: July 10, 2014Date of Patent: October 20, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seong Il Kim, Dong Min Kang, Sang Heung Lee, Ho Kyun Ahn, Hyung Sup Yoon, Byoung Gue Min, Jong Won Lim
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Patent number: 9165896Abstract: The present invention relates to a GaN transistor, and a method of fabricating the same, in which a structure of a bonding pad is improved by forming an ohmic metal layer at edges of the bonding pad of a source, a drain, and a gate so as to be appropriate to wire-bonding or a back-side via-hole forming process. Accordingly, adhesive force between a metal layer of the bonding pad and a GaN substrate is enhanced by forming the ohmic metal at the edges of the bonding pad during manufacturing of the GaN transistor, thereby minimizing a separation phenomenon of a pad layer during the wire-bonding or back-side via-hole forming process, and improving reliability of a device.Type: GrantFiled: August 7, 2014Date of Patent: October 20, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hae Cheon Kim, Ho Kyun Ahn, Byoung Gue Min, Hyung Sup Yoon, Jong Won Lim
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Patent number: 9159612Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.Type: GrantFiled: September 9, 2013Date of Patent: October 13, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Byoung-Gue Min, Sang Choon Ko, Jong-Won Lim, Hokyun Ahn, Hyung Sup Yoon, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 9136396Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.Type: GrantFiled: May 30, 2013Date of Patent: September 15, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sang Choon Ko, Jae Kyoung Mun, Byoung-Gue Min, Young Rak Park, Hokyun Ahn, Jeong-Jin Kim, Eun Soo Nam
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Publication number: 20150236108Abstract: Disclosed are a semiconductor device having a stable gate structure, and a manufacturing method thereof, in which a gate structure is stabilized by additionally including a plurality of gate feet under a gate head in a width direction of the gate head so as to serve as supporters in a gate structure including a fine gate foot having a length of 0.2 ?m or smaller, and the gate head having a predetermined size. Accordingly, it is possible to prevent the gate electrode of the semiconductor device from collapsing, and improve reliability of the semiconductor device during or after the process of the semiconductor device.Type: ApplicationFiled: July 10, 2014Publication date: August 20, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Seong Il KIM, Dong Min KANG, Sang Heung LEE, Ho Kyun AHN, Hyung Sup YOON, Byoung Gue MIN, Jong Won LIM
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Publication number: 20150206847Abstract: The present invention relates to a GaN transistor, and a method of fabricating the same, in which a structure of a bonding pad is improved by forming an ohmic metal layer at edges of the bonding pad of a source, a drain, and a gate so as to be appropriate to wire-bonding or a back-side via-hole forming process. Accordingly, adhesive force between a metal layer of the bonding pad and a GaN substrate is enhanced by forming the ohmic metal at the edges of the bonding pad during manufacturing of the GaN transistor, thereby minimizing a separation phenomenon of a pad layer during the wire-bonding or back-side via-hole forming process, and improving reliability of a device.Type: ApplicationFiled: August 7, 2014Publication date: July 23, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Hae Cheon KIM, Ho Kyun AHN, Byoung Gue MIN, Hyung Sup YOON, Jong Won LIM
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Publication number: 20150194494Abstract: Disclosed are a field effect transistor for high voltage driving including a gate electrode structure in which a gate head extended in a direction of a drain is supported by a field plate embedded under a region of the gate head so as to achieve high voltage driving, and a manufacturing method thereof. Accordingly, the gate head extended in the direction of the drain is supported by the field plate electrically spaced by using an insulating layer, so that it is possible to stably manufacture a gate electrode including the extended gate head, and gate resistance is decreased by the gate head extended in the direction of the drain and an electric field peak value between the gate and the drain is decreased by the gate electrode including the gate head extended in the direction of the drain and the field plate proximate to the gate, thereby achieving an effect in that a breakdown voltage of a device is increased.Type: ApplicationFiled: April 2, 2014Publication date: July 9, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Ho Kyun AHN, Hae Cheon KIM, Zin Sig KIM, Sang Heung LEE, Byoung Gue MIN, Hyung Sup YOON, Dong Min KANG, Seong Il KIM, Jong Min LEE, Jong Won LIM, Yong Hwan KWON, Eun Soo NAM
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Publication number: 20150177309Abstract: A test device includes: a testing unit connected with a measurement line, and configured to apply bias to the measurement line and measure the measurement line; a plurality of switching units configured to electrically connect the measurement line and the plurality of samples; and a control unit configured to sequentially turn on the plurality of switching units to sequentially apply the bias to the plurality of samples. The control unit determines whether a corresponding device sample has a defect based on a first measurement value according to measurement by the testing unit when the bias is applied to each of the plurality of samples.Type: ApplicationFiled: June 11, 2014Publication date: June 25, 2015Inventors: Jong Min LEE, Chull Won JU, Byoung Gue MIN
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Publication number: 20150171188Abstract: A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a ?-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the ?-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.Type: ApplicationFiled: February 27, 2015Publication date: June 18, 2015Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hyung Sup YOON, Byoung-Gue MIN, Jong-Won LIM, Hokyun AHN, Seong-Il Kim, Sang Heung LEE, Dong Min KANG, Chull Won JU, Jae Kyoung MUN
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Publication number: 20150144961Abstract: A high frequency device includes: a capping layer formed on an epitaxial structure; source and drain electrodes formed on the capping layer; a multilayer insulating pattern formed on entire surfaces of the source and drain electrodes and the capping layer in a step shape; a T-shaped gate passing through the multilayer insulating pattern and the capping layer to be in contact with the epitaxial structure; and a passivation layer formed along entire surfaces of the T-shaped gate and the multilayer insulating pattern.Type: ApplicationFiled: February 7, 2014Publication date: May 28, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Hyung Sup YOON, Byoung Gue MIN, Ho Kyun AHN, Jong Won LIM, Dong Min KANG, Jong Min LEE
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Patent number: 8941231Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.Type: GrantFiled: July 10, 2013Date of Patent: January 27, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Young Rak Park, Sang Choon Ko, Byoung-Gue Min, Jong-Won Lim, Hokyun Ahn, Sung-Bum Bae, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 8853821Abstract: Provided are vertical capacitors and methods of forming the same. The formation of the vertical capacitor may include forming input and output electrodes on a top surface of a substrate, etching a bottom surface of the substrate to form via electrodes, and then, forming a dielectric layer between the via electrodes. As a result, a vertical capacitor with high capacitance can be provided in a small region of the substrate.Type: GrantFiled: September 14, 2012Date of Patent: October 7, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Seong-il Kim, Sang-Heung Lee, Jong-Won Lim, Hyung Sup Yoon, Jongmin Lee, Byoung-Gue Min, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 8841154Abstract: Disclosed is a method of manufacturing a field effect type compound semiconductor device in which leakage current of a device is decreased and breakdown voltage is enhanced.Type: GrantFiled: June 12, 2013Date of Patent: September 23, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Hyung Sup Yoon, Byoung-Gue Min, Jong-Won Lim, Ho Kyun Ahn, Jong Min Lee, Seong-il Kim, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20140167175Abstract: A field effect transistor is provided. The transistor may include a source electrode and a drain electrode provided spaced apart from each other on a substrate and a ‘+’-shaped gate electrode provided on a portion of the substrate located between the source and drain electrodes.Type: ApplicationFiled: June 11, 2013Publication date: June 19, 2014Inventors: Seong-Il KIM, Jong-Won Lim, Dong Min Kang, Sang-Heung Lee, Hyung Sup Yoon, Chull Won Ju, Byoung-Gue Min, Jongmin Lee, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20140167070Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.Type: ApplicationFiled: July 10, 2013Publication date: June 19, 2014Inventors: Young Rak PARK, Sang Choon Ko, Byoung-Gue Min, Jong-Won Lim, Hokyun Ahn, Sung-Bum Bae, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20140159050Abstract: A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a ?-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the ?-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.Type: ApplicationFiled: July 3, 2013Publication date: June 12, 2014Inventors: Hyung Sup YOON, Byoung-Gue Min, Jong-Won Lim, Hokyun Ahn, Seong-ll Kim, Sang-Heung Lee, Dong Min Kang, Chull Won Ju, Jae Kyoung Mun
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Publication number: 20140159049Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.Type: ApplicationFiled: May 30, 2013Publication date: June 12, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Sang Choon KO, Jae Kyoung Mun, Byoung-Gue Min, Young Rak Park, Hokyun Ahn, Jeong-Jin Kim, Eun Soo Nam
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Publication number: 20140152338Abstract: Provided is a low-cost and high-efficient system for measuring reliability of an electronic device. According to the present invention, a single input power source for applying power to an input terminal of a plurality of electronic device samples and a single output power source for applying power to an output terminal of the plurality of electronic device samples are provided. Further, an input switch having first switches of which the number corresponds to the number of the plurality of electronic device samples, the input switch being installed between the input power source and the input terminal so that the first switches are selectively switched to apply input power; and an output switch having second switches of which the number corresponds to the number of the plurality of electronic device samples, the output switch being installed between the output power source and the output terminal so that the second switches are selectively switched to apply output power are provided.Type: ApplicationFiled: July 25, 2013Publication date: June 5, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Jongmin LEE, Byoung-Gue Min, Chull Won Ju