Patents by Inventor Byoung Gue Min
Byoung Gue Min has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8722474Abstract: Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.Type: GrantFiled: August 23, 2012Date of Patent: May 13, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Hyung Sup Yoon, Byoung-Gue Min, Jong Min Lee, Seong-Il Kim, Dong Min Kang, Ho Kyun Ahn, Jong-Won Lim, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20140103539Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.Type: ApplicationFiled: September 9, 2013Publication date: April 17, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Byoung-Gue MIN, Sang Choon KO, Jong-Won Lim, Hokyun AHN, Hyung Sup YOON, Jae Kyoung MUN, Eun Soo NAM
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Patent number: 8692371Abstract: Disclosed are a semiconductor apparatus and a manufacturing method thereof. The manufacturing method of the semiconductor apparatus includes: forming a semiconductor chip on a semiconductor substrate; adhering a carrier wafer with a plurality of through holes onto the semiconductor chip; polishing the semiconductor substrate; forming a first via hole at the rear side of the polished semiconductor substrate; forming a first metal layer below the polished semiconductor substrate and at the first via hole; and removing the carrier wafer from the polished semiconductor substrate.Type: GrantFiled: July 16, 2012Date of Patent: April 8, 2014Assignee: Electronics and Telecommunications Research InstituteInventor: Byoung-Gue Min
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Publication number: 20140035044Abstract: Disclosed are a field-effect transistor and a manufacturing method thereof. The disclosed field-effect transistor includes: a semiconductor substrate; a source ohmic metal layer formed on one side of the semiconductor substrate; a drain ohmic metal layer formed on another side of the semiconductor substrate; a gate electrode formed between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; an insulating film formed on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and a plurality of field electrodes formed on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.Type: ApplicationFiled: October 9, 2013Publication date: February 6, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Hokyun AHN, Jong-Won LIM, Hyung Sup YOON, Byoung-Gue MIN, Sang-Heung LEE, Hae Cheon KIM, Eun Soo NAM
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Publication number: 20140017885Abstract: Disclosed is a method of manufacturing a field effect type compound semiconductor device in which leakage current of a device is decreased and breakdown voltage is enhanced.Type: ApplicationFiled: June 12, 2013Publication date: January 16, 2014Inventors: Hyung Sup YOON, Byoung-gue Min, Jong-Won Lim, Ho Kyun Ahn, Jong Min Lee, Seong-il Kim, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 8586462Abstract: Disclosed are a method of manufacturing a field-effect transistor. The disclosed method includes: providing a semiconductor substrate; forming a source ohmic metal layer on one side of the semiconductor substrate; forming a drain ohmic metal layer on another side of the semiconductor substrate; forming a gate electrode between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; forming an insulating film on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and forming a plurality of field electrodes on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.Type: GrantFiled: November 30, 2011Date of Patent: November 19, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Hokyun Ahn, Jong-Won Lim, Hyung Sup Yoon, Byoung-Gue Min, Sang-Heung Lee, Hae Cheon Kim, Eun Soo Nam
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Publication number: 20130146944Abstract: Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.Type: ApplicationFiled: August 23, 2012Publication date: June 13, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hyung Sup YOON, Byoung-Gue Min, Jong Min Lee, Seong-II Kim, Dong Min Kang, Ho Kyun Ahn, Jong-Won Lim, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20130134554Abstract: Provided are vertical capacitors and methods of forming the same. The formation of the vertical capacitor may include forming input and output electrodes on a top surface of a substrate, etching a bottom surface of the substrate to form via electrodes, and then, forming a dielectric layer between the via electrodes. As a result, a vertical capacitor with high capacitance can be provided in a small region of the substrate.Type: ApplicationFiled: September 14, 2012Publication date: May 30, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seong-il KIM, Sang-Heung LEE, Jong-Won LIM, Hyung Sup YOON, Jongmin LEE, Byoung-Gue MIN, Jae Kyoung MUN, Eun Soo NAM
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Publication number: 20130026631Abstract: Disclosed are a semiconductor apparatus and a manufacturing method thereof. The manufacturing method of the semiconductor apparatus includes: forming a semiconductor chip on a semiconductor substrate; adhering a carrier wafer with a plurality of through holes onto the semiconductor chip; polishing the semiconductor substrate; forming a first via hole at the rear side of the polished semiconductor substrate; forming a first metal layer below the polished semiconductor substrate and at the first via hole; and removing the carrier wafer from the polished semiconductor substrate.Type: ApplicationFiled: July 16, 2012Publication date: January 31, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventor: Byoung-Gue MIN
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Patent number: 8338241Abstract: Provided are a method of manufacturing a normally-off mode high frequency device structure and a method of simultaneously manufacturing a normally-on mode high frequency device structure and a normally-off mode high frequency device structure on a single substrate.Type: GrantFiled: October 28, 2011Date of Patent: December 25, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Hyung Sup Yoon, Byoung-Gue Min, Hokyun Ahn, Sang-Heung Lee, Hae Cheon Kim
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Publication number: 20120153361Abstract: Disclosed are a field-effect transistor and a manufacturing method thereof. The disclosed field-effect transistor includes: a semiconductor substrate; a source ohmic metal layer formed on one side of the semiconductor substrate; a drain ohmic metal layer formed on another side of the semiconductor substrate; a gate electrode formed between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; an insulating film formed on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and a plurality of field electrodes formed on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.Type: ApplicationFiled: November 30, 2011Publication date: June 21, 2012Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hokyun Ahn, Jong-Won Lim, Hyung Sup Yoon, Byoung-Gue Min, Sang-Heung Lee, Hae Cheon Kim, Eun Soo Nam
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Publication number: 20120142148Abstract: Provided are a method of manufacturing a normally-off mode high frequency device structure and a method of simultaneously manufacturing a normally-on mode high frequency device structure and a normally-off mode high frequency device structure on a single substrate.Type: ApplicationFiled: October 28, 2011Publication date: June 7, 2012Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hyung Sup YOON, Byoung-Gue Min, Hokyun Ahn, Sang-Heung Lee, Hae Cheon Kim
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Publication number: 20120098099Abstract: Provided are a compound semiconductor device and a method of manufacturing the same. The semiconductor device includes: a substrate including a first region and a second region; a transistor including first to third conductive impurity layers stacked on the substrate of the first region; and a variable capacitance diode spaced apart from the transistor of the first region and including the first and second conductive impurity layers stacked on the substrate of the second region.Type: ApplicationFiled: July 29, 2011Publication date: April 26, 2012Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jongmin LEE, Byoung-Gue Min, Seong-il Kim, Hyung Sup Yoon, Hae Cheon Kim, Eun Soo Nam
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Patent number: 8130041Abstract: Provided is a power amplifier device. The power amplifier device includes: a cutoff unit cutting off a direct current (DC) component of a signal delivered from a signal input terminal; a circuit protecting unit connected to the cutoff unit and stabilizing a signal delivered from the cutoff unit; and an amplification unit connected to the circuit protecting unit and amplifying a signal delivered from the circuit protecting unit, wherein the amplification unit comprises a plurality of transistors connected in parallel to the circuit protecting unit and the circuit protecting unit comprises resistors connected to between bases of the plurality of transistors.Type: GrantFiled: December 3, 2010Date of Patent: March 6, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Seong-Il Kim, Jongmin Lee, Byoung-Gue Min, Hyung Sup Yoon, Hae Cheon Kim, Eun Soo Nam
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Patent number: 8124489Abstract: Provided are a monolithic microwave integrated circuit device and a method for forming the same. The method includes: forming an sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer on a Heterojunction Bipolar Transistor (HBT) region and a PIN diode region of a substrate; forming an emitter pattern and an emitter cap pattern in the HBT region and exposing the base layer by patterning the emitter layer and the emitter cap layer; and forming an intrinsic region by doping a portion of the collector layer of the PIN diode region with a first type impurity, the PIN diode region being spaced apart from the HBT region.Type: GrantFiled: July 8, 2010Date of Patent: February 28, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Byoung-Gue Min, Jongmin Lee, Seong-Il Kim, Hyung Sup Yoon
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Patent number: 7986211Abstract: Provided is an inductor. The inductor includes a first to a fourth conductive terminals formed in one direction within a semiconductor substrate, a first conductive line formed on one side of the semiconductor substrate and electrically connected to the second and third conductive terminals interiorly positioned among the first to fourth conductive terminals, a second conductive line formed on the one side of the semiconductor substrate and electrically connected to the first and fourth conductive terminals exteriorly positioned among the first to fourth conductive terminals, and a third conductive line formed on the other side of the semiconductor substrate and electrically connected to the first and third conductive terminals among the first to fourth conductive terminals.Type: GrantFiled: December 14, 2010Date of Patent: July 26, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Seong-il Kim, Jongmin Lee, Byoung-Gue Min, Hyung Sup Yoon, Hae Cheon Kim, Eun Soo Nam
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Publication number: 20110140825Abstract: Provided is an inductor. The inductor includes a first to a fourth conductive terminals formed in one direction within a semiconductor substrate, a first conductive line formed on one side of the semiconductor substrate and electrically connected to the second and third conductive terminals interiorly positioned among the first to fourth conductive terminals, a second conductive line formed on the one side of the semiconductor substrate and electrically connected to the first and fourth conductive terminals exteriorly positioned among the first to fourth conductive terminals, and a third conductive line formed on the other side of the semiconductor substrate and electrically connected to the first and third conductive terminals among the first to fourth conductive terminals.Type: ApplicationFiled: December 14, 2010Publication date: June 16, 2011Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seong-il KIM, Jongmin Lee, Byoung-Gue Min, Hyung Sup Yoon, Hae Cheon Kim, Eun Soo Nam
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Publication number: 20110140175Abstract: Provided are a monolithic microwave integrated circuit device and a method for forming the same. The method includes: forming an sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer on a Heterojunction Bipolar Transistor (HBT) region and a PIN diode region of a substrate; forming an emitter pattern and an emitter cap pattern in the HBT region and exposing the base layer by patterning the emitter layer and the emitter cap layer; and forming an intrinsic region by doping a portion of the collector layer of the PIN diode region with a first type impurity, the PIN diode region being spaced apart from the HBT region.Type: ApplicationFiled: July 8, 2010Publication date: June 16, 2011Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Byoung-Gue MIN, Jongmin Lee, Seong-ll Kim, Hyung Sup Yoon
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Publication number: 20110133843Abstract: Provided is a power amplifier device. The power amplifier device includes: a cutoff unit cutting off a direct current (DC) component of a signal delivered from a signal input terminal; a circuit protecting unit connected to the cutoff unit and stabilizing a signal delivered from the cutoff unit; and an amplification unit connected to the circuit protecting unit and amplifying a signal delivered from the circuit protecting unit, wherein the amplification unit comprises a plurality of transistors connected in parallel to the circuit protecting unit and the circuit protecting unit comprises resistors connected to between bases of the plurality of transistors.Type: ApplicationFiled: December 3, 2010Publication date: June 9, 2011Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seong-Il KIM, Jongmin Lee, Byoung-Gue Min, Hyung Sup Yoon, Hae Cheon Kim, Eun Soo Nam
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Publication number: 20100133586Abstract: Provided are a heterojunction bipolar transistor and a method of forming the same.Type: ApplicationFiled: May 8, 2009Publication date: June 3, 2010Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Byoung-Gue MIN, Jong-Min Lee, Seong-II Kim, Kyung-Ho Lee, Hyung-Sup Yoon, Eun-Soo Nam