Abstract: A display device includes a plurality of pixels disposed in an display area, and a pixel driver connected to at least two of the pixels, wherein the pixel driver drives the at least two pixels, where a portion of the pixel driver is disposed in the display area, and the display device includes the display area, on which an image is displayed, and a non-display area, on which no image is displayed.

Abstract: A liquid crystal display device includes upper and lower pixels; gate lines in electrical connection with the adjacent pixels and extending in a row direction, and data lines which cross the gate lines; and a reference voltage line including a vertical portion which passes through the adjacent pixels, and horizontal portions which alternately extend from the vertical portion. Each of the adjacent pixels includes first and second thin film transistors (TFTs) each in electrical connection with a gate line and a data line which correspond to a respective pixel; and a pixel electrode including a first subpixel electrode in connection with an output terminal of the first TFT, and a second subpixel electrode in connection with an output terminal of the second TFT. The horizontal portions of the reference voltage line are in electrical connection with the second subpixel electrodes of the adjacent pixels.

Abstract: A display device includes a plurality of pixels disposed in an display area, and a pixel driver connected to at least two of the pixels, wherein the pixel driver drives the at least two pixels, where a portion of the pixel driver is disposed in the display area, and the display device includes the display area, on which an image is displayed, and a non-display area, on which no image is displayed.

Abstract: Embodiments of the present disclosure provide a thin-film transistor (TFT) panel structured to prevent the deterioration of image quality due to the luminance change of backlight.

Abstract: A substantially rectangular display panel includes a first edge extending in a first major axis direction of the rectangular shape and a second edge extending in a second major axis direction of the rectangular shape, the second direction being different from the first direction. The display panel includes: a plurality of gate lines extending in the first direction; and a gate lines driver including a plurality of main stages sequentially connected to each other and configured for outputting gate signals to the gate lines, where the plurality of stages further includes one or more dummy stages arranged in a row along the second edge and not connected to the plurality of gate lines, and where a layout arrangement of a plurality of thin film transistors included in the main stage is different from a corresponding layout arrangement of corresponding thin film transistors included in the at least one dummy stage.

Abstract: A display apparatus includes a display panel comprising a plurality of gate lines connected to a plurality of pixel rows, a plurality of data lines connected to a plurality of a pixel columns, at least one dummy pixel row disposed in a peripheral area surrounding a display area in which the plurality of pixel rows and the plurality of a pixel columns are disposed, and at least one dummy gate line connected to the dummy pixel row and a data driver circuit configured to provide the dummy pixel row with a dummy data signal, the dummy data signal having a level that differs from a data signal of a pixel column adjacent to the dummy pixel row.

Abstract: A method of driving a gate line includes: charging one of a scan start signal and a carry signal provided from a previous stage to a first node of a present stage; outputting a gate signal through a gate node of the present stage by pulling up a high level of a first clock signal at the first node to boost up a voltage potential of the first node; discharging the voltage potential of the first node and a voltage potential of the gate node to hold the first node and the gate node at a first power voltage as the first clock signal is shifted to a low level; and receiving a voltage potential signal of a second node of the previous stage, the second node holding a gate signal outputted from the previous stage, to reduce a ripple generated at the first node.

Abstract: A substantially rectangular display panel includes a first edge extending in a first major axis direction of the rectangular shape and a second edge extending in a second major axis direction of the rectangular shape, the second direction being different from the first direction. The display panel includes: a plurality of gate lines extending in the first direction; and a gate lines driver including a plurality of main stages sequentially connected to each other and configured for outputting gate signals to the gate lines, where the plurality of stages further includes one or more dummy stages arranged in a row along the second edge and not connected to the plurality of gate lines, and where a layout arrangement of a plurality of thin film transistors included in the main stage is different from a corresponding layout arrangement of corresponding thin film transistors included in the at least one dummy stage.

Abstract: A display device that may be driven at both frequencies of 120 Hz and 240 Hz, includes a plurality of pixels arranged in a column direction and a row direction, a plurality of data lines connected with one of the pixels of a j-th row (‘j’ is a natural number) and one of the pixels of a (j+1)-th row in k-th column (‘k’ is a natural number), and connected with one of the pixels of a (j+2)-th row and one of the pixels of a (j+3)-th row in (k?1)-th column, a first gate circuit part configured to apply a gate signal to a (4m?3)-th gate line row (‘m’ is a natural number), a second gate circuit part configured to apply a gate signal to a (4m?2)-th gate line row, a third gate circuit part configured to apply a gate signal to a (4m?1)-th gate line row and a fourth gate circuit part configured to apply a gate signal to a 4m-th gate line row.

Abstract: Provided are a liquid crystal display panel and a manufacturing method thereof, and more particularly, a liquid crystal display panel including white pixels and a manufacturing method thereof. The liquid crystal display panel includes: a first substrate and a second substrate facing each other; a liquid crystal layer positioned between the first substrate and the second substrate; a plurality of color filters positioned on the first substrate and representing different colors from each other, in which at least two of the plurality of color filters overlap with each other on the first substrate to form an overlapping portion, and the overlapping portion forms a first spacer; a transparent filter positioned on the first substrate and positioned in a transmitting area of a white pixel; and a second spacer including the same material as the transparent filter.

Abstract: One or more embodiments of the present invention are directed to a liquid crystal display including: a first substrate and a second substrate facing each other; a first color pixel area, a second color pixel area, a third color pixel area, and a white pixel area on any one of the first substrate and the second substrate; and a liquid crystal layer between the first substrate and the second substrate. A first color filter is disposed in each of the first color pixel area and the white pixel area, and each of the first, second, third, and white pixel areas includes a plurality of domains, each two adjacent domains having a boundary between them, and the first color filter is disposed at at least one of the boundaries between the domains in the white pixel area.

Abstract: A gate driver that comprises n shift registers, wherein n is an integer equal to or larger than 1, each of the n shift registers includes; a start stage which outputs a gate signal and starts its operation in response to a start signal, and a plurality of subsequent stages which are connected to each other in sequence, and which sequentially output a plurality of gate signals in response to a signal output from the start stage, wherein at least one stage of the plurality of subsequent stages is reset by the start signal.

Abstract: A gate driving circuit including first through (N)th stages is provided. An (M)th stage of the first through (N)th stages includes a pull-up control part, a pull-up part, a carry holding part, a carry part, and a first pull-down part. The pull-up control part applies a second node signal of a second node to a first node in response to the second node signal. The pull-up part outputs a clock signal as an (M)th gate output signal in response to the first node signal. The carry holding part applies the (M)th gate output signal to the second node in response to the (M)th gate output signal. The carry part outputs the clock signal as an (M)th carry signal in response to the first node signal. The first pull-down part pulls down the (M)th gate output signal to a first off voltage.

Abstract: A display device, includes: a plurality of gate lines which transmits a gate signal; a plurality of data lines which transmits a positive-polarity data voltage and a negative-polarity data voltage; a first color pixel including a first switching element connected to the gate line and the data line and a first capacitor connected to the first switching element, where the first color pixel displays a first color; and a second color pixel including a second switching element connected to the gate line and the data line and a second capacitor connected to the second switching element, where the second color pixel displays a second color different from the first color, where an optimum common voltage of the first color pixel is lower than an optimum common voltage of the second color pixel.

Abstract: A liquid crystal display includes a first substrate, a first gate line disposed on the first substrate, a second gate line disposed on the first substrate, a data line disposed on the first substrate, a reference voltage line disposed on the first substrate and extending substantially to be parallel to the data line, a first subpixel electrode disposed in a pixel area on the first substrate, a second subpixel electrode disposed in the pixel area on the first substrate, a first switching element connected to the first gate line, the data line and the first subpixel electrode, a second switching element connected to the first gate line, the data line and the second subpixel electrode, and a third switching element connected to the first subpixel electrode and the reference voltage line.

Abstract: Provided are a gate driving apparatus and a display device including the same. The gate driving apparatus includes a plurality of stages arranged sequentially, each stage is adapted to output a gate signal and including first output lines and a second output line, wherein the first output lines are electrically connected to a gate line corresponding to each of the stages and are adapted to transmit the gate signal to a plurality of pixels coupled to the gate line, the second output line is adapted to transmit the gate signal to a preceding stage of each of the stages, and the first output lines and the second output line share one contact pad.

Abstract: The present invention relates to a thin film transistor array panel including: a substrate; gate lines formed on the substrate; and a gate driver formed on the substrate to apply gate signals to the gate lines. The gate driver includes a first wire and a second wire to transmit different signals, and at least one of the first wire and the second wire includes a static electricity preventing structure to prevent static electricity from accumulating between the first wire and the second wire.

Abstract: A photomask includes; a source electrode pattern including; a first electrode portion which extends in a first direction, a second electrode portion which extends in the first direction and is substantially parallel to the first electrode portion, and a third electrode portion which extends from a first end of the first electrode portion to a first end of the second electrode portion and is rounded with a first curvature, a drain electrode pattern which extends in the first direction and is disposed between the first electrode portion and the second electrode portion, wherein an end of the drain electrode pattern is rounded to correspond to the third electrode portion; and a channel region pattern which is disposed between the source electrode pattern and the drain electrode pattern, wherein a center location of the first curvature and a center location of the rounded portion of the end of the drain electrode pattern are the same.

Abstract: An array substrate includes a base substrate and a contact part. The contact part is disposed on the base substrate. The contact part includes a first metal pattern, a disconnection control pattern and a connecting pattern. The second metal pattern is disposed on a layer different from the first metal pattern, the disconnection control pattern overlaps a side surface of the second metal pattern and a connecting pattern is formed on the first and second metal patterns and the disconnection control pattern and connects the first metal pattern with the second metal pattern.

Abstract: A liquid crystal display device includes upper and lower pixels; gate lines in electrical connection with the adjacent pixels and extending in a row direction, and data lines which cross the gate lines; and a reference voltage line including a vertical portion which passes through the adjacent pixels, and horizontal portions which alternately extend from the vertical portion. Each of the adjacent pixels includes first and second thin film transistors (TFTs) each in electrical connection with a gate line and a data line which correspond to a respective pixel; and a pixel electrode including a first subpixel electrode in connection with an output terminal of the first TFT, and a second subpixel electrode in connection with an output terminal of the second TFT. The horizontal portions of the reference voltage line are in electrical connection with the second subpixel electrodes of the adjacent pixels.