Abstract: A memory system includes a representative memory device directly outputting a representative data strobe signal, at least one non-representative memory device outputting a non-representative data strobe signal through the representative memory device, and a controller generating an internal delay clock signal synchronized with the representative data strobe signal. The controller outputs a test mode code defining a delay time using the internal delay clock signal as a reference signal. The at least one non-representative memory device adjusts a phase of the non-representative data strobe signal such that the non-representative data strobe signal has a delay time corresponding to the test mode code.

Abstract: A memory system includes a representative memory device directly outputting a representative data strobe signal, at least one non-representative memory device outputting a non-representative data strobe signal through the representative memory device, and a controller generating an internal delay clock signal synchronized with the representative data strobe signal. The controller outputs a test mode code defining a delay time using the internal delay clock signal as a reference signal. The at least one non-representative memory device adjusts a phase of the non-representative data strobe signal such that the non-representative data strobe signal has a delay time corresponding to the test mode code.

Abstract: A semiconductor device includes a plurality of first pads, a plurality of data input and output units suitable for transmitting a data between a plurality of global lines and the plurality of first pads, respectively, a connection control unit suitable for coupling the plurality of first pads to each other in a test operation period, and a test operation unit suitable for controlling the plurality of data input and output units to transmit a test data in a set order through the plurality of first pads coupled to each other in the test operation period.

Abstract: A semiconductor system includes a master chip and a plurality of slave chips. The master chip controls internal voltage levels of the respective slave chips based on signals outputted from the plurality of slave chips such that, by referring to any one slave chip of the plurality of slave chips, internal voltage levels of remaining slave chips are controlled.

Abstract: A semiconductor integrated circuit device includes a first circuit block configured to receive data from a plurality of data I/O (input/output) lines and output test data in a test mode, and a second circuit block configured to connect the plurality of data I/O lines and the first circuit block, output the data of the plurality of data I/O lines in a normal mode and output the test data provided from the first circuit block in the test mode.

Abstract: A semiconductor device may include a first channel configured to output a first rising clock, a first falling clock, first rising data, and first falling data. The semiconductor device may include a second channel configured to output a second rising clock, a second falling clock, second rising data, and second falling data. The semiconductor device may include an I/O control unit configured to receive the first rising clock, the first falling clock, the first rising data, and the first falling data, generate output data, and externally output the output data through a pad unit or receive the second rising clock, the second falling clock, the second rising data, and the second falling data, generate the output data, and externally output the output data through the pad unit.

Abstract: A data transmission circuit may include first, second, and third pads, generate a pull-up code and a pull-down code in accordance with a resistance value between the third pad and a ground terminal, and drive data with drivability adjustable by the pull-up code and the pull-down code to output the data. The data reception circuit may include a resistor coupling circuit coupled between the first pad and the second pad to include a second resistance value, include an external resistor coupled to the third pad through a first wiring resistor having a first resistance value, and receive the data through a second wiring resistor.

Abstract: A semiconductor device includes a buffer block configured to generate a strobe signal by buffering an external strobe signal inputted through a first pad, output the strobe signal to a first node of a first input/output line, generate data by buffering external data inputted through a second pad, and output the data to a second node of a second input/output line; a first channel configured to store the data loaded on the second input/output line in synchronization with the strobe signal loaded on the first input/output line; and a second channel configured to store the data loaded on the second input/output line in synchronization with the strobe signal loaded on the first input/output line.

Abstract: A semiconductor device includes a buffer block configured to generate a strobe signal by buffering an external strobe signal inputted through a first pad, output the strobe signal to a first node of a first input/output line, generate data by buffering external data inputted through a second pad, and output the data to a second node of a second input/output line; a first channel configured to store the data loaded on the second input/output line in synchronization with the strobe signal loaded on the first input/output line; and a second channel configured to store the data loaded on the second input/output line in synchronization with the strobe signal loaded on the first input/output line.

Abstract: A semiconductor device may include a first channel configured to output a first rising clock, a first falling clock, first rising data, and first falling data. The semiconductor device may include a second channel configured to output a second rising clock, a second falling clock, second rising data, and second falling data. The semiconductor device may include an I/O control unit configured to receive the first rising clock, the first falling clock, the first rising data, and the first falling data, generate output data, and externally output the output data through a pad unit or receive the second rising clock, the second falling clock, the second rising data, and the second falling data, generate the output data, and externally output the output data through the pad unit.

Abstract: A semiconductor device includes a first data input/output unit storing first internal input data in a first cell block in response to a first shift data strobe signal generated by shifting a first data strobe signal in a test mode, a second data input/output unit storing second internal input data in a second cell block in response to a second shift data strobe signal generated by shifting a second data strobe signal in the test mode, and a connector electrically coupling the first data input/output unit to the second data input/output unit in the test mode.

Abstract: Semiconductor device includes a first data input/output (I/O) portion suitable for storing data inputted thereto through a first pad in a first cell block in synchronization with a test data strobe signal or a first data strobe signal and suitable for outputting the data stored in the first cell block to the first pad, a second data I/O portion suitable for storing data inputted thereto through a second pad in a second cell block in synchronization with the test data strobe signal or a second data strobe signal and suitable for outputting the data stored in the second cell block to the second pad, and a connection portion suitable for electrically connecting the first and second pads to each other in a test mode. Related semiconductor systems are also provided.

Abstract: A semiconductor device includes a first data input/output unit storing first internal input data in a first cell block in response to a first shift data strobe signal generated by shifting a first data strobe signal in a test mode, a second data input/output unit storing second internal input data in a second cell block in response to a second shift data strobe signal generated by shifting a second data strobe signal in the test mode, and a connector electrically coupling the first data input/output unit to the second data input/output unit in the test mode.

Abstract: A semiconductor integrated circuit device includes a first circuit block configured to receive data from a plurality of data I/O (input/output) lines and output test data in a test mode, and a second circuit block configured to connect the plurality of data I/O lines and the first circuit block, output the data of the plurality of data I/O lines in a normal mode and output the test data provided from the first circuit block in the test mode.

Abstract: Semiconductor device includes a first data input/output (I/O) portion suitable for storing data inputted thereto through a first pad in a first cell block in synchronization with a test data strobe signal or a first data strobe signal and suitable for outputting the data stored in the first cell block to the first pad, a second data I/O portion suitable for storing data inputted thereto through a second pad in a second cell block in synchronization with the test data strobe signal or a second data strobe signal and suitable for outputting the data stored in the second cell block to the second pad, and a connection portion suitable for electrically connecting the first and second pads to each other in a test mode. Related semiconductor systems are also provided.

Abstract: A semiconductor system includes a master chip and a plurality of slave chips. The master chip controls internal voltage levels of the respective slave chips based on signals outputted from the plurality of slave chips such that, by referring to any one slave chip of the plurality of slave chips, internal voltage levels of remaining slave chips are controlled.

Abstract: A semiconductor device includes two or more memory chips electrically coupled. Each of the memory chips includes global lines, a MUX unit, a selection unit, and an output unit. The global lines transmit data stored in memory cells. The MUX unit receives the data loaded onto the global lines to output a test data. The selection unit is inserted into two or more of the global lines and configured to output the test data instead of the data loaded onto the two or more global lines, in a test mode. The output unit is coupled to the global lines and is configured to output the data in a normal mode, and output the test data received from any one of the two or more global lines connected to the selection unit to an I/O pad based on information about the memory chip in a test mode.

Abstract: A semiconductor device includes a plurality of first pads, a plurality of data input and output units suitable for transmitting a data between a plurality of global lines and the plurality of first pads, respectively, a connection control unit suitable for coupling the plurality of first pads to each other in a test operation period, and a test operation unit suitable for controlling the plurality of data input and output units to transmit a test data in a set order through the plurality of first pads coupled to each other in the test operation period.

Abstract: A semiconductor memory system includes a semiconductor memory configured to provide an external circuit with a plurality of refresh characteristic information and perform an auto-refresh operation in response to a plurality of auto-refresh commands, and a memory controller configured to provide the semiconductor memory with the plurality of auto-refresh commands generated according to the plurality of refresh characteristic information.

Abstract: A semiconductor apparatus includes a data output unit and a test output unit. The data output unit outputs a plurality of data, through a plurality of data lines, to a plurality of input/output pads. The test output unit receives one of the plurality of data and a plurality of output data, which is output to the plurality of input/output pads, and outputs the received data to a probe pad in a probe test mode.