Abstract: Redundancy circuits for accessing the stored data in the memory banks are provided in a semiconductor memory. First and second memory banks, each has 2N number of redundancy lines. Only N number of redundancy lines in each memory bank is utilized during normal operations. During normal operations, a first redundancy control block provides N number of redundancy signals to the first memory bank. A second redundancy control block provides N number of redundancy signals to the second memory bank. An address signal switching unit receives memory bank failure signals. During normal operations, the address signal switching unit multiplexes the N number of redundancy signals from the redundancy control block to the N number of redundancy lines of the corresponding memory bank.

Abstract: A low power semiconductor memory device having a normal mode and a partial array self refresh mode. The device includes a plurality of banks including a memory cell array; a memory control unit for generating a pre-bank selection signal related to the bank selection; a bank selection signal generating unit for generating a bank selection signal practically selecting a bank by using the pre-bank selection signal in the normal mode and for generating a bank selection signal according to refresh properties of the bank without using the pre-bank selection signal in the partial array self refresh mode.

Abstract: Disclosed is a redundancy efficiency increasing circuit of semiconductor memory device. The circuit comprises 2N banks each having 2M redundancy lines; 2N redundancy control blocks; and an address signal switch unit for receiving first and second control signals, and an address signal. If the first signal is enabled, a bank address signal selecting (2n−1)th bank is provided to redundancy control blocks corresponding to (2n−1)th bank and (2n)th bank. If the second signal is enabled, a bank address signal selecting (2n)th bank is provided to the redundancy control blocks corresponding to (2n−1)th bank and (2n)th bank. If the first and second signals are enabled, a bank address signal selecting (2n−1)th bank is provided to the redundancy control block corresponding to (2n−1)th bank, and a bank address signal selecting (2n)th bank is provided to the redundancy control block corresponding to (2n)th bank.

Abstract: A low power semiconductor memory device having a normal mode and a partial array self refresh mode. The device includes a plurality of banks including a memory cell array; a memory control unit for generating a pre-bank selection signal related to the bank selection; a bank selection signal generating unit for generating a bank selection signal practically selecting a bank by using the pre-bank selection signal in the normal mode and for generating a bank selection signal according to refresh properties of the bank without using the pre-bank selection signal in the partial array self refresh mode.