Abstract: A multi-chip semiconductor apparatus includes a plurality of semiconductor chips electrically connected and stacked. Each of the semiconductor chips trims a voltage level used in the semiconductor chip in response to a chip select signal.

Abstract: A semiconductor apparatus includes first and second chips sharing first and second data channels. The first and second chips output normal data of the respective chips through the first and second data channels in a normal operation, and the first chip outputs test data of the first chip through the first data channel, and the second chip outputs test data of the second chip through the second data channel in a test operation.

Abstract: A semiconductor device includes two or more memory chips electrically coupled. Each of the memory chips includes global lines, a MUX unit, a selection unit, and an output unit. The global lines transmit data stored in memory cells. The MUX unit receives the data loaded onto the global lines to output a test data. The selection unit is inserted into two or more of the global lines and configured to output the test data instead of the data loaded onto the two or more global lines, in a test mode. The output unit is coupled to the global lines and is configured to output the data in a normal mode, and output the test data received from any one of the two or more global lines connected to the selection unit to an I/O pad based on information about the memory chip in a test mode.

Abstract: A multi-chip semiconductor apparatus includes a plurality of semiconductor chips electrically connected and stacked. Each of the semiconductor chips trims a voltage level used in the semiconductor chip in response to a chip select signal.

Abstract: An apparatus for outputting data in a semiconductor integrated circuit includes a clock generation block configured to activate a first clock signal for outputting a data signal and a second clock signal for outputting a data strobe signal based on a predetermined timing, and a data output block configured to latch a pre-data signal and a pre-data strobe signal in response to the first clock signal and the second clock signal, respectively.

Abstract: A semiconductor apparatus includes first and second chips sharing first and second data channels. The first and second chips output normal data of the respective chips through the first and second data channels in a normal operation, and the first chip outputs test data of the first chip through the first data channel, and the second chip outputs test data of the second chip through the second data channel in a test operation.

Abstract: A semiconductor integrated circuit includes a bump pad through which data is outputted, a probe test pad having a larger size than the bump pad, a first output drive unit configured to drive the bump pad at a first drivability in response to output data, a second output drive unit configured to drive the probe test pad at a second drivability higher than the first drivability in response to the output data, and a multiplexing unit configured to transfer the output data to the first output drive unit or the second output drive unit in response to a test mode signal.

Abstract: A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.

Abstract: A semiconductor integrated circuit includes a first node through which an input signal passes and an adjustment block including at least one delay unit electrically connected to the first node. The semiconductor integrated circuit also includes a correction block configured to generate a control signal which controls whether to activate a delay unit.

Abstract: A voltage stabilization circuit includes a control signal generating unit to generate a control signal that is enabled when a supply voltage is unstable and a voltage level maintaining unit for selectively controlling total capacitance of a plurality of capacitors to stabilize the supply voltage in response to the control signal.

Abstract: A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.

Abstract: A semiconductor integrated circuit includes a first bump pad and a second bump pad configured to perform at least one of a data input operation and a data output operation in a normal mode; a probe pad configured to perform at least one of a data input operation and a data output operation in a test mode; a data output unit configured to communicate a data to one of the first bump pad and the probe pad; a data input unit configured to communicate a data from one of the second bump pad and the probe pad; a first switching unit configured to connect the probe pad and the data output unit in response to a test mode signal; and a second switching unit configured to connect the probe pad and the data input unit in response to the test mode signal.

Abstract: A semiconductor integrated circuit includes a bump pad through which data is outputted, a probe test pad having a larger size than the bump pad, a first output drive unit configured to drive the bump pad at a first drivability in response to output data, a second output drive unit configured to drive the probe test pad at a second drivability higher than the first drivability in response to the output data, and a multiplexing unit configured to transfer the output data to the first output drive unit or the second output drive unit in response to a test mode signal.

Abstract: A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.

Abstract: A semiconductor integrated circuit includes: a first node through which an input signal passes; an adjustment block including at least one delay unit electrically connected to the first node; and a correction block configured to generate a control signal which controls whether to activate a delay unit.

Abstract: A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.

Abstract: An apparatus for outputting data in a semiconductor integrated circuit includes a clock generation block configured to activate a first clock signal for outputting a data signal and a second clock signal for outputting a data strobe signal based on a predetermined timing, and a data output block configured to latch a pre-data signal and a pre-data strobe signal in response to the first clock signal and the second clock signal, respectively.

Abstract: A stable voltage generating circuit for a delay locked loop for generating a stable internal voltage for a delay locked loop and a semiconductor memory device including the same, and a method of generating a stable voltage for a delay locked loop is disclosed. The voltage generating circuit includes a first detector which compares a feedback voltage that represents the internal voltage for the delay locked loop with a reference voltage and outputs the comparison result as a first detection signal. A second detector detects the escape timing of a power down mode to provide a second detection signal having a configurable enable width interval after the escape timing of the power down mode. Finally, the voltage generating circuit includes a voltage driver which drives and outputs the internal voltage either the first detection signal or the second detection signal is enabled to maintain a stable internal voltage level.

Abstract: An output driver of a semiconductor memory apparatus comprises a voltage dividing block configured to generate divide voltages by dividing an internal voltage, a threshold voltage detecting block configured to generate a detecting voltage corresponding to a change in a threshold voltage of a transistor, a drive capability control signal generating block 300 configured to generate a compare signal by comparing the levels of the detecting voltage with the divide voltage and generate a control signal in response to an input signal when the compare signal is enabled, and a drive capability controlling block comprising a driver configured to perform a driving operation in response to the input signal, and a control driver configured to perform a driving operation in response to the control signal.

Abstract: A voltage stabilization circuit includes a control signal generating unit not generating a control signal that is enabled when a supply voltage is unstable and a voltage level maintaining unit for selectively controlling total capacitance of a plurality of capacitors to stabilize the supply voltage in response to the control signal.