Patents by Inventor Byung Hak Lee
Byung Hak Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240109595Abstract: A frame structure for a vehicle includes: an inner panel connected to a side member and defining an inner side of a rear part of the side member; an outer panel connected to a rear side of the side member and coupled to an outer side of the inner panel defining a closed cross-section together with the inner panel and defining an outer side of the rear part of the side member; an opening portion formed below the inner and outer panels partially opening the closed cross-section so that a front end of a rear suspension arm can be inserted into the opening portion; and a reinforcing member disposed in the opening portion defining the closed cross-section together with the outer panel and the inner panel and configured to close an internal space in the outer and inner panels.Type: ApplicationFiled: January 25, 2023Publication date: April 4, 2024Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATIONInventors: Won Hae Lee, Nam Ho Kim, Mi Ran Park, Ha Yeon Kwon, Byung Joo Chung, Seung Hak Lee, Min Seok Kim
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Patent number: 11939000Abstract: A frame structure for a purpose built vehicle (PBV) includes: two main side members extending while gradually rising toward a front of the PBV and extending in a front/rear direction to be disposed on either side of the PBV; two auxiliary side members respectively extending in a front/rear direction to be disposed on a lower side of the two main side members; a front cross member connecting the two auxiliary side members in a lateral direction of the PBV; and a plurality of vertical members respectively connecting the main side members and the auxiliary side members in a vertical direction.Type: GrantFiled: September 19, 2022Date of Patent: March 26, 2024Assignees: HYUNDAI MOTOR COMPANY, KIA CORPORATIONInventors: Won Hae Lee, Nam Ho Kim, Byung Joo Chung, Seung Hak Lee, Min Seok Kim
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Patent number: 11935703Abstract: A multilayer electronic component has a body and a non-conductive resin layer. The non-conductive resin layer includes a body cover portion disposed in a region of an external surface of the body in which an electrode layer of an external electrode is not disposed, and an extending portion extending from the body cover portion between the electrode layer and a conductive resin layer of the external electrode, to thereby suppress arc discharge, improve bending strength, and improve moisture resistance.Type: GrantFiled: January 9, 2023Date of Patent: March 19, 2024Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jae Seok Yi, Jung Min Kim, Bon Seok Koo, Chang Hak Choi, Il Ro Lee, Byung Woo Kang, San Kyeong, Hae Sol Kang
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Patent number: 11926364Abstract: A frame for a purpose-built vehicle (PBV) includes: a front part frame positioned at a front side of a vehicle; a rear part frame positioned at a rear side of the vehicle; and a center part frame. The center part frame has a rectangular planar shape and is coupled between the front part frame and the rear part frame.Type: GrantFiled: October 28, 2022Date of Patent: March 12, 2024Assignees: HYUNDAI MOTOR COMPANY, KIA CORPORATIONInventors: Nam Ho Kim, Won Hae Lee, Byung Joo Chung, Seung Hak Lee, Min Seok Kim
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Publication number: 20230181292Abstract: Provided is a surface-treated implant structure. The implant structure according to an aspect includes a fixture acting as an artificial tooth root, and the nano-protrusions included in the outer peripheral surface of the fixture exhibit a certain level of height, depth, and aspect ratio.Type: ApplicationFiled: November 30, 2021Publication date: June 15, 2023Applicant: B2LAB CO.,LTD.Inventors: Bo Su JEONG, Byung Hak LEE
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Patent number: 8470703Abstract: Methods of forming a semiconductor device include providing a substrate having an area including a source and a drain region of a transistor. A nickel (Ni) metal film is formed on the substrate area including the source and the drain region. A first heat-treatment process is performed including heating the substrate including the metal film from a first temperature to a second temperature at a first ramping rate and holding the substrate including the metal film at the second temperature for a first period of time. A second heat-treatment process is then performed including heating the substrate including the metal film from a third temperature to a fourth temperature at a second ramping rate and holding the substrate at the fourth temperature for a second period of time. The fourth temperature is different from the second temperature and the second period of time is different from the first period of time.Type: GrantFiled: May 11, 2011Date of Patent: June 25, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Hak Lee, Yu-Gyun Shin, Sang-Woo Lee, Sun-Ghil Lee, Jin-Bum Kim, Joon-Gon Lee
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Patent number: 8466052Abstract: A method of fabricating a semiconductor device can include forming a trench in a semiconductor substrate, forming a first conductive layer on a bottom surface and side surfaces of the trench, and selectively forming a second conductive layer on the first conductive layer to be buried in the trench. The second conductive layer may be formed selectively on the first conductive layer by using an electroless plating method or using a metal organic chemical vapor deposition (MOCVD) or an atomic layer deposition (ALD) method.Type: GrantFiled: February 11, 2010Date of Patent: June 18, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-min Baek, Hee-sook Park, Seong-hwee Cheong, Gil-heyun Choi, Byung-hak Lee, Tae-ho Cha, Jae-hwa Park, Su-kyoung Kim
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Publication number: 20110306205Abstract: Methods of forming a semiconductor device include providing a substrate having an area including a source and a drain region of a transistor. A nickel (Ni) metal film is formed on the substrate area including the source and the drain region. A first heat-treatment process is performed including heating the substrate including the metal film from a first temperature to a second temperature at a first ramping rate and holding the substrate including the metal film at the second temperature for a first period of time. A second heat-treatment process is then performed including heating the substrate including the metal film from a third temperature to a fourth temperature at a second ramping rate and holding the substrate at the fourth temperature for a second period of time. The fourth temperature is different from the second temperature and the second period of time is different from the first period of time.Type: ApplicationFiled: May 11, 2011Publication date: December 15, 2011Inventors: Byung-Hak Lee, Yu-Gyun Shin, Sang-Woo Lee, Sun-Ghil Lee, Jin-Bum Kim, Joon-Gon Lee
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Patent number: 8034701Abstract: Methods of forming a gate electrode can be provided by forming a trench in a substrate, conformally forming a polysilicon layer to provide a polysilicon conformal layer in the trench defining a recess surrounded by the polysilicon conformal layer, wherein the polysilicon conformal layer is formed to extend upwardly from a surface of the substrate to have a protrusion and the protrusion has a vertical outer sidewall adjacent the surface of the substrate, forming a tungsten layer in the recess to form an upper surface that includes an interface between the polysilicon conformal layer and the tungsten layer, and forming a capping layer being in direct contact with top surfaces of the polysilicon conformal layer and the tungsten layer without any intervening layers.Type: GrantFiled: July 31, 2009Date of Patent: October 11, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Hak Lee, Chang-Won Lee, Hee-Sook Park, Woong-Hee Sohn, Sun-Pil Youn, Jong-ryeol Yoo
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Patent number: 7989892Abstract: A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer.Type: GrantFiled: June 12, 2009Date of Patent: August 2, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Ho Cha, Seong-Hwee Cheong, Jong-Min Baek, Jae-Hwa Park, Gil-Heyun Choi, Byung-Hee Kim, Byung-Hak Lee, Hee-Sook Park
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Patent number: 7879737Abstract: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.Type: GrantFiled: May 24, 2010Date of Patent: February 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Woong-Hee Sohn, Gil-Heyun Choi, Byung-Hee Kim, Byung-Hak Lee, Tae-Ho Cha, Hee-Sook Park, Jae-Hwa Park, Geum-Jung Seong
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Patent number: 7875939Abstract: In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.Type: GrantFiled: May 1, 2009Date of Patent: January 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Sook Park, Gil-Heyun Choi, Chang-Won Lee, Byung-Hak Lee, Sun-Pil Youn, Dong-Chan Lim, Jae-Hwa Park, Jang-Hee Lee, Woong-Hee Sohn
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Publication number: 20110003455Abstract: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPDX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPDX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.Type: ApplicationFiled: May 24, 2010Publication date: January 6, 2011Inventors: Woong-Hee SOHN, Gil-Heyun CHOI, Byung-Hee KIM, Byung-Hak LEE, Tae-Ho CHA, Hee-Sook PARK, Jae-Hwa PARK, Geum-Jung SEONG
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Patent number: 7781849Abstract: Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer.Type: GrantFiled: December 3, 2008Date of Patent: August 24, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-min Baek, Seong-hwee Cheong, Gil-heyun Choi, Tae-ho Cha, Hee-sook Park, Byung-hak Lee, Jae-hwa Park
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Publication number: 20100210105Abstract: A method of fabricating a semiconductor device can include forming a trench in a semiconductor substrate, forming a first conductive layer on a bottom surface and side surfaces of the trench, and selectively forming a second conductive layer on the first conductive layer to be buried in the trench. The second conductive layer may be formed selectively on the first conductive layer by using an electroless plating method or using a metal organic chemical vapor deposition (MOCVD) or an atomic layer deposition (ALD) method.Type: ApplicationFiled: February 11, 2010Publication date: August 19, 2010Inventors: Jong-min Baek, Hee-sook Park, Seong-hwee Cheong, Gil-heyun Choi, Byung-hak Lee, Tae-ho Cha, Jae-hwa Park, Su-kyoung Kim
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Patent number: 7772637Abstract: Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.Type: GrantFiled: March 10, 2009Date of Patent: August 10, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Woong-Hee Sohn, Chang-Won Lee, Sun-Pil Youn, Gil-Heyun Choi, Byung-Hak Lee, Jong-Ryeol Yoo, Hee-Sook Park
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Patent number: 7759263Abstract: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.Type: GrantFiled: May 31, 2007Date of Patent: July 20, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Woong-Hee Sohn, Gil-Heyun Choi, Byung-Hee Kim, Byung-Hak Lee, Tae-Ho Cha, Hee-Sook Park, Jae-Hwa Park, Geum-Jung Seong
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Patent number: 7696552Abstract: A semiconductor device includes a first conductive layer on a semiconductor substrate, a dielectric layer including a high-k dielectric material on the first conductive layer, a second conductive layer including polysilicon doped with P-type impurities on the dielectric layer, and a third conductive layer including a metal on the second conductive layer. In some devices, a first gate structure is formed in a main cell region and includes a tunnel oxide layer, a floating gate, a first high-k dielectric layer, and a control gate. The control gate includes a layer of polysilicon doped with P-type impurities and a metal layer. A second gate structure is formed outside the main cell region and includes a tunnel oxide layer, a conductive layer, and a metal layer. A third gate structure is formed in a peripheral cell region and includes a tunnel oxide, a conductive layer, and a high-k dielectric layer having a width narrower than the conductive layer. Method embodiments are also disclosed.Type: GrantFiled: September 15, 2005Date of Patent: April 13, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Pil Youn, Chang-Won Lee, Woong-Hee Sohn, Gil-Heyun Choi, Jong-Ryeol Yoo, Dong-Chan Lim, Jae-Hwa Park, Byung-Hak Lee, Hee-Sook Park
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Publication number: 20090315091Abstract: A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layerType: ApplicationFiled: June 12, 2009Publication date: December 24, 2009Inventors: Tae-Ho Cha, Seong-Hwee Cheong, Jong-Min Baek, Jae-Hwa Park, Gil-Heyun Choi, Byung-Hee Kim, Byung-Hak Lee, Hee-Sook Park
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Publication number: 20090298273Abstract: Methods of forming a gate electrode can be provided by forming a trench in a substrate, conformally forming a polysilicon layer to provide a polysilicon conformal layer in the trench defining a recess surrounded by the polysilicon conformal layer, wherein the polysilicon conformal layer is formed to extend upwardly from a surface of the substrate to have a protrusion and the protrusion has a vertical outer sidewall adjacent the surface of the substrate, forming a tungsten layer in the recess to form an upper surface that includes an interface between the polysilicon conformal layer and the tungsten layer, and forming a capping layer being in direct contact with top surfaces of the polysilicon conformal layer and the tungsten layer without any intervening layers.Type: ApplicationFiled: July 31, 2009Publication date: December 3, 2009Inventors: Byung-Hak Lee, Chang-Won Lee, Hee-Sook Park, Woong-Hee Sohn, Sun-Pil Youn, Jong-ryeol Yoo