Patents by Inventor Byung Hak Lee
Byung Hak Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7696552Abstract: A semiconductor device includes a first conductive layer on a semiconductor substrate, a dielectric layer including a high-k dielectric material on the first conductive layer, a second conductive layer including polysilicon doped with P-type impurities on the dielectric layer, and a third conductive layer including a metal on the second conductive layer. In some devices, a first gate structure is formed in a main cell region and includes a tunnel oxide layer, a floating gate, a first high-k dielectric layer, and a control gate. The control gate includes a layer of polysilicon doped with P-type impurities and a metal layer. A second gate structure is formed outside the main cell region and includes a tunnel oxide layer, a conductive layer, and a metal layer. A third gate structure is formed in a peripheral cell region and includes a tunnel oxide, a conductive layer, and a high-k dielectric layer having a width narrower than the conductive layer. Method embodiments are also disclosed.Type: GrantFiled: September 15, 2005Date of Patent: April 13, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Pil Youn, Chang-Won Lee, Woong-Hee Sohn, Gil-Heyun Choi, Jong-Ryeol Yoo, Dong-Chan Lim, Jae-Hwa Park, Byung-Hak Lee, Hee-Sook Park
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Publication number: 20090315091Abstract: A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layerType: ApplicationFiled: June 12, 2009Publication date: December 24, 2009Inventors: Tae-Ho Cha, Seong-Hwee Cheong, Jong-Min Baek, Jae-Hwa Park, Gil-Heyun Choi, Byung-Hee Kim, Byung-Hak Lee, Hee-Sook Park
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Publication number: 20090298273Abstract: Methods of forming a gate electrode can be provided by forming a trench in a substrate, conformally forming a polysilicon layer to provide a polysilicon conformal layer in the trench defining a recess surrounded by the polysilicon conformal layer, wherein the polysilicon conformal layer is formed to extend upwardly from a surface of the substrate to have a protrusion and the protrusion has a vertical outer sidewall adjacent the surface of the substrate, forming a tungsten layer in the recess to form an upper surface that includes an interface between the polysilicon conformal layer and the tungsten layer, and forming a capping layer being in direct contact with top surfaces of the polysilicon conformal layer and the tungsten layer without any intervening layers.Type: ApplicationFiled: July 31, 2009Publication date: December 3, 2009Inventors: Byung-Hak Lee, Chang-Won Lee, Hee-Sook Park, Woong-Hee Sohn, Sun-Pil Youn, Jong-ryeol Yoo
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Publication number: 20090256177Abstract: In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.Type: ApplicationFiled: May 1, 2009Publication date: October 15, 2009Inventors: Hee-Sook PARK, Gil-Heyun CHOI, Chang-Won LEE, Byung-Hak LEE, Sun-Pil YOUN, Dong-Chan LIM, Jae-Hwa PARK, Jang-Hee LEE, Woong-Hee SOHN
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Patent number: 7582924Abstract: Semiconductor devices and methods of fabricating the same are provided. A gate insulating film is provided on a semiconductor substrate. A polymetal gate electrode is provided on the gate insulating film. The polymetal gate electrode includes a conductive polysilicon film on the gate insulating film, a first metal silicide film on the conductive polysilicon film, a barrier film on the first metal silicide film, and a metal film on the barrier film. The barrier film includes a titanium nitride (TiN) film on the first metal silicide film and a buffer layer between the TiN film and the metal film.Type: GrantFiled: April 7, 2006Date of Patent: September 1, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Hak Lee, Dong-Chan Lim, Gil-Heyun Choi, Hee-Sook Park
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Patent number: 7582931Abstract: A gate electrode of a transistor can include an interface between a polysilicon conformal layer and a tungsten layer thereon in a trench in a substrate and a capping layer extending across the trench and covering the interface. Related methods are also disclosed.Type: GrantFiled: June 3, 2005Date of Patent: September 1, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Hak Lee, Chang-Won Lee, Hee-Sook Park, Woong-Hee Sohn, Sun-Pil Youn, Jong-ryeol Yoo
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Publication number: 20090189229Abstract: Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer.Type: ApplicationFiled: December 3, 2008Publication date: July 30, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Jong-min Baek, Seong-hwee Cheong, Gil-heyun Choi, Tae-ho Cha, Hee-sook Park, Byung-hak Lee, Jae-hwa Park
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Publication number: 20090173986Abstract: Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.Type: ApplicationFiled: March 10, 2009Publication date: July 9, 2009Inventors: Woong-Hee Sohn, Chang-Won Lee, Sun-Pil Youn, Gil-Heyun Choi, Byung-Hak Lee, Jong-Ryeol Yoo, Hee-Sook Park
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Patent number: 7550353Abstract: One embodiment of a method for forming a semiconductor device can include forming a gate pattern on a semiconductor substrate and performing a selective re-oxidation process on the gate pattern in gas ambient including hydrogen, oxygen, and nitrogen. When the gate pattern includes a tunnel insulation layer, a metal nitride layer and a metal layer, the selective re-oxidation process heals the etching damage of a gate pattern and simultaneously prevents oxidation of the metal nitride layer and a tungsten electrode.Type: GrantFiled: March 13, 2007Date of Patent: June 23, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Hak Lee, Woong-Hee Sohn, Jae-Hwa Park, Gil-Heyun Choi, Byung-Hee Kim, Hee-Sook Park
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Patent number: 7544597Abstract: In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.Type: GrantFiled: January 17, 2006Date of Patent: June 9, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Sook Park, Gil-Heyun Choi, Chang-Won Lee, Byung-Hak Lee, Sun-Pil Youn, Dong-Chan Lim, Jae-Hwa Park, Jang-Hee Lee, Woong-Hee Sohn
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Patent number: 7534709Abstract: Embodiments of the present invention include semiconductor devices that can be made with relatively low resistance, and methods of forming the semiconductor devices. A resistance reducing layer is formed between a polysilicon layer and a metal layer. As a result, an interface resistance between the polysilicon layer and the metal layer is greatly reduced and a distribution of the interface resistance is very uniform. As a result, a conductive structure including the resistance reducing layer has a greatly reduced sheet resistance to improve electrical characteristics of a semiconductor device having the conductive structure.Type: GrantFiled: September 23, 2005Date of Patent: May 19, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hwa Park, Gil-Heyun Choi, Chang-Won Lee, Byung-Hak Lee, Hee-Sook Park, Woong-Hee Sohn, Jong-Ryeol Yoo, Sun-Pil Yun, Jang-Hee Lee, Dong-Chan Lim
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Publication number: 20090101984Abstract: A semiconductor device may include a gate dielectric film on a semiconductor substrate and/or a gate electrode. The gate electrode may include a first metal film, a first metal silicide film, and/or a conductive polysilicon film sequentially stacked on the gate dielectric film.Type: ApplicationFiled: December 20, 2007Publication date: April 23, 2009Inventors: Byung-hak Lee, Woong-hee Sohn, Jae-hwa Park, Gil-heyun Choi, Byung-hee Kim, Hee-sook Park
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Patent number: 7521316Abstract: Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.Type: GrantFiled: September 7, 2005Date of Patent: April 21, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Woong-Hee Sohn, Chang-Won Lee, Sun-Pil Youn, Gil-Heyun Choi, Byung-Hak Lee, Jong-Ryeol Yoo, Hee-Sook Park
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Patent number: 7499005Abstract: A plasma display panel includes a first substrate and a second substrate facing each other with a plurality of discharge cells formed therebetween. A plurality of scan electrodes and a plurality of sustain electrodes are alternately arranged on the second substrate, and a discharge cell comprises a first sustain electrode, a second sustain electrode, and a scan electrode.Type: GrantFiled: December 21, 2004Date of Patent: March 3, 2009Assignee: Samsung SDI Co., Ltd.Inventors: Woo-Joon Chung, Jin-Sung Kim, Seung-Hun Chae, Byung Hak Lee
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Patent number: 7416968Abstract: Methods of forming field effect transistors according to embodiments of the invention include forming a conductive gate electrode (e.g., polysilicon gate electrode) on a semiconductor substrate and forming a first metal layer on the conductive gate electrode. This first metal layer may include a material selected from a group consisting of nickel, cobalt, titanium, tantalum and tungsten. The first metal layer and the conductive gate electrode are thermally treated for a sufficient duration to convert a first portion of the conductive gate electrode into a first metal silicide region. The first metal layer and the first metal silicide region are then removed to expose a second portion of the conductive gate electrode. A second metal layer is then formed on the second portion of the conductive gate electrode. This second metal layer may include a material selected from a group consisting of nickel, cobalt, titanium, tantalum and tungsten.Type: GrantFiled: September 20, 2005Date of Patent: August 26, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Su Kim, Jong-Ho Yun, Byung-Hak Lee, Eun-Ji Jung, Gil-Heyun Choi
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Patent number: 7371669Abstract: In a method for forming a gate in a semiconductor device, a first preliminary gate structure is formed on a substrate. The first preliminary gate structure includes a gate oxide layer, a polysilicon layer pattern and a tungsten layer pattern sequentially stacked on the substrate. A primary oxidation process is performed using oxygen radicals at a first temperature for adjusting a thickness of the gate oxide layer to form a second preliminary gate structure having tungsten oxide. The tungsten oxide is reduced to a tungsten material using a gas containing hydrogen to form a gate structure. The tungsten oxide may not be formed on the gate structure so that generation of the whiskers may be suppressed. Thus, a short between adjacent wirings may not be generated.Type: GrantFiled: November 18, 2005Date of Patent: May 13, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Pil Youn, Chang-Won Lee, Woong-Hee Sohn, Gil-Heyun Choi, Jong-Ryeol Yoo, Jang-Hee Lee, Jae-Hwa Park, Dong-Chan Lim, Byung-Hak Lee, Hee-Sook Park
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Publication number: 20080102615Abstract: One embodiment of a method for forming a semiconductor device can include forming a gate pattern on a semiconductor substrate and performing a selective re-oxidation process on the gate pattern in gas ambient including hydrogen, oxygen, and nitrogen. When the gate pattern includes a tunnel insulation layer, a metal nitride layer and a metal layer, the selective re-oxidation process heals the etching damage of a gate pattern and simultaneously prevents oxidation of the metal nitride layer and a tungsten electrode.Type: ApplicationFiled: March 13, 2007Publication date: May 1, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byung-Hak LEE, Woong-Hee SOHN, Jae-Hwa PARK, Gil-Heyun CHOI, Byung-Hee KIM, Hee-Sook PARK
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Publication number: 20080093660Abstract: A flash memory device includes a semiconductor substrate, a gate insulating layer having a first width formed on the semiconductor substrate to trap carriers tunneled from the semiconductor substrate and a metal electrode on the gate insulating layer to receive a voltage required for tunneling. The metal electrode having a second width smaller than the first width. The flash memory device further includes a sidewall spacer surrounding a side surface of the metal electrode to prevent oxidation of the metal electrode.Type: ApplicationFiled: January 12, 2007Publication date: April 24, 2008Inventors: Hee-Sook Park, Byung-Hak Lee, Tae-Ho Cha, Woong-Hee Sohn, Jang-Hee Lee, Jae-Hwa Park
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Publication number: 20080014700Abstract: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.Type: ApplicationFiled: May 31, 2007Publication date: January 17, 2008Inventors: Woong-Hee Sohn, Gil-Heyun Choi, Byung-Hee Kim, Byung-hak Lee, Tae-Ho Cha, Hee-Sook Park, Jae-Hwa Park, Geum-Jung Seong
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Patent number: 7244511Abstract: A single-side embossed color steel sheet, and a method for manufacturing the same are disclosed. The steel sheet comprises a steel sheet substrate, a zinc or zinc alloy-plated layer, a non-chromate or chromate pretreated layer, a primary coat paint layer of modified epoxy or modified polyester, a color base paint layer, a printed layer, and a top coat clear paint layer. The printed layer exhibits a feeling of solidity with various feelings of texture and colors. The top coat clear paint layer serves to protect the printed layer from contaminants. The color steel sheet exhibits a remarkably enhanced feeling of solidity at an irregular surface thereof, and has enhanced contaminant resistance properties and environmental friendliness, thereby satisfying requirements for aesthetic design and functionality of products.Type: GrantFiled: January 4, 2006Date of Patent: July 17, 2007Assignee: Union Steel Manufacturing Co., Ltd.Inventors: Jang Hyun Choi, Sung Su Jun, Sang Hoon Park, Won Young Lee, Byung Hak Lee