Abstract: An image sensor is provided. The image sensor includes a photodiode disposed in a semiconductor substrate and a first device isolating layer formed having an impurity with a conductivity type in the semiconductor substrate adjacent to the photodiode. The image sensor further includes a second device isolating layer composed of an insulating layer that covers the first device isolating layer. In addition, the image sensor further includes an interlayer insulating layer formed on the second device isolating layer and which is composed of a material with refractivity greater than that of the second device isolating layer.

Abstract: An image sensor and methods of manufacturing the same are provided. An isolation layer of a CMOS image sensor including an active pixel region and a logic circuit region and methods of manufacturing the same are also provided. A method of manufacturing an image sensor having a unit pixel, which includes a photodiode for picking up light and a transistor group for transferring and processing data picked up by the photodiode, is also provided. The methods may include forming a pad oxide layer on a semiconductor substrate. A buffer layer may be formed on an upper surface of the pad oxide layer. An oxidation preventing mask may be formed to expose a device-mounting isolation region. After oxidizing the buffer layer exposed by the oxidation preventing mask, the remaining oxidation preventing mask, buffer layer and pad oxide layer may be removed to form an isolation layer for defining an active region where the photodiode and the transistor group maybe formed.

Abstract: According to some embodiments, methods of fabricating a complementary metal oxide semiconductor (CMOS) type semiconductor device having dual gates are provided. The method includes forming an insulated first gate electrode on the P-type well, and an insulated second initial gate electrode on the N-type well. A first lower interlayer insulating layer exposing a top surface of the first gate electrode is formed on the P-type well while a second lower interlayer insulating layer exposing a top surface of the second initial gate electrode is formed on the N-type well. P-type impurity ions are selectively implanted into the second initial gate electrode to form a second gate electrode. A first ion implantation mask pattern is formed over the first gate electrode while a second ion implantation mask pattern is formed over the second gate electrode. The second lower interlayer insulating layer is etched, using the second ion implantation mask pattern as an etch mask, to expose a top surface of the N-type well.

Abstract: An integrated circuit device includes a CMOS image sensor and a MIM capacitor therein. The CMOS image sensor includes a transfer gate electrode on a semiconductor substrate and a P-N junction photodiode within the semiconductor substrate. The photodiode is located adjacent a first side of the transfer gate electrode. A floating diffusion region is also provided within the semiconductor substrate. This floating diffusion region is located adjacent a second side of the transfer gate electrode. An interlayer insulating layer is provided on the semiconductor substrate. The interlayer insulating layer extends opposite the transfer gate electrode, the P-N junction photodiode and the floating diffusion region. An optical shielding layer of a first material is provided on the interlayer insulating layer. The optical shielding layer has a single opening therein, which extends opposite the P-N junction photodiode. This single opening inhibits optical crosstalk between adjacent unit cells within the sensor.

Abstract: Dark current caused by a crystalline defect in an interfacial surface of a device isolating layer is prevented according to an image sensor and a method of manufacturing the same. A first device isolating layer adjacent to a photodiode disposed on an upper surface of a semiconductor substrate protrudes from the semiconductor substrate. A side surface of the first device isolating layer is covered by a first spacer with a refractivity greater than that of the first device isolating layer. The photodiode is insulated by the device isolating layer protruding from the semiconductor substrate to prevent the dark current. By forming the spacer on the sidewall of the device isolating layer to attain total reflection, efficiency of light incident to the photodiode is improved.

Abstract: A method of manufacturing an image sensor comprises forming an isolation layer defining an active region in a semiconductor substrate using a first mask pattern formed on the semiconductor substrate, forming a first ion implantation mask pattern by reducing a width of the first mask pattern to expose an edge portion of the active region around the isolation layer, forming a first hole accumulation region by implanting a first conductive type of impurity ions into the edge portion of the active region using the first ion implantation mask pattern, forming a second ion implantation mask pattern covering the isolation layer and the first hole accumulation region, and forming a photodiode by implanting a second conductive type of impurity ions into a region of the semiconductor substrate using the second ion implantation mask pattern, wherein at least a portion of the region is surrounded by the first hole accumulation region in the active region.

Abstract: A method and an apparatus for tracking a location of a UE by using an integrated GPS and TDOA scheme in a mobile communication network are provided. A GPS position solution of the UE is obtained using GPS code information. TDOA position solutions are obtained using pilot signal transmission times of BSs and pilot signal reception times of the UE, and an average value of the TDOA position solutions is calculated. The GPS position solution is subtracted from the average to obtain a position error value, and an iterative method using a least square method is performed for the position error value to correct the position error. The corrected position error value is added to the average value of the TDOA position solutions to obtain a more precise position solution.

Abstract: Wirings including first conductive layer patterns and insulating mask layer patterns are formed on a substrate. Insulating spacers are formed on sidewalls of the wirings. Self-aligned contact pads including portions of a second conductive layer are formed to contact with surfaces of the insulating spacers and to fill up a gap between the wirings. An interlayer dielectric layer is formed on the substrate where the contact pads are formed and is then partially etched to form contact holes exposing the contact pads. A selective epitaxial silicon layer is formed on the contact pads exposed through the contact holes to cover the insulating mask layer patterns. Thus, a short-circuit between the lower wiring and an upper wiring formed in the contact holes is prevented.

Abstract: The present invention provides a method of fabricating a capacitor for a semiconductor device. The method includes: forming sequentially a lower electrode and a dielectric layer having a high dielectric constant over a semiconductor substrate which have gone through predetermined processes; forming sequentially a first metal layer and a poly-silicon layer over the dielectric layer; forming an upper electrode pattern by pattering the poly-silicon layer and the first metal layer; forming a second metal layer covering the upper electrode pattern on an entire surface of the semiconductor substrate; and forming an upper electrode constituted with the second metal layer, the poly-silicon layer and the first metal layer by patterning the second metal layer so that the second metal layer is connected with the first metal layer.

Abstract: A semiconductor device capable of preventing an electrical short between contacts and their adjacent contact pads and a method of manufacturing the same are provided. A first interlayer insulating layer is formed on the semiconductor substrate including the active region. Contact pads pass through the first interlayer insulating layer and contact with the active region. Contacts are formed on the contact pads and are connected to a conductive layer disposed above the contacts. The contact pads have a height lower than a top surface of the first interlayer insulating layer such that the contact pads have smaller thickness than the first interlayer insulating layer.

Abstract: Wirings including first conductive layer patterns and insulating mask layer patterns are formed on a substrate. Insulating spacers are formed on sidewalls of the wirings. Self-aligned contact pads including portions of a second conductive layer are formed to contact with surfaces of the insulating spacers and to fill up a gap between the wirings. An interlayer dielectric layer is formed on the substrate where the contact pads are formed and is then partially etched to form contact holes exposing the contact pads. A selective epitaxial silicon layer is formed on the contact pads exposed through the contact holes to cover the insulating mask layer patterns. Thus, a short-circuit between the lower wiring and an upper wiring formed in the contact holes is prevented.

Abstract: An integrated circuit device includes a semiconductor substrate that has a cell region and a peripheral region that surrounds the cell region. A plurality of capacitors that include a plurality of lower electrodes, respectively, are disposed in the cell region. Supporters connect adjacent ones of the plurality of lower electrodes to provide structural support and stability to the lower electrodes.

Abstract: According to some embodiments, methods of fabricating a complementary metal oxide semiconductor (CMOS) type semiconductor device having dual gates are provided. The method includes forming an insulated first gate electrode on the P-type well, and an insulated second initial gate electrode on the N-type well. A first lower interlayer insulating layer exposing a top surface of the first gate electrode is formed on the P-type well while a second lower interlayer insulating layer exposing a top surface of the second initial gate electrode is formed on the N-type well. P-type impurity ions are selectively implanted into the second initial gate electrode to form a second gate electrode. A first ion implantation mask pattern is formed over the first gate electrode while a second ion implantation mask pattern is formed over the second gate electrode. The second lower interlayer insulating layer is etched, using the second ion implantation mask pattern as an etch mask, to expose a top surface of the N-type well.

Abstract: A channel estimation method in a Multiple Input Multiple Output (MIMO) mobile communication system having a plurality of transmission antennas and a plurality of reception antennas is provided. In a method of transmitting, by a transmitter, channel estimation signals for channel estimation at a receiver, the transmission antennas transmit the same channel estimation signals for a first frame transmission duration, and transmit predetermined channel estimation signals corresponding to the number of the transmission antennas for a second frame transmission duration.

Abstract: A semiconductor memory device and a method for manufacturing the same are provided.

Abstract: A method for soft-combining MBMS (Multimedia Broadcast/Multicast Service) data in an asynchronous mobile communication system including a user equipment (UE) and a radio network controller (RNC), wherein the system provides an MBMS service. In the method, the RNC measures a round trip delay (RTD) for a primary cell in which the UE is located, and an RTD for each of the neighbor cells neighboring the primary cell. The RNC transmits the MBMS data at the same transmission time by considering the RTDs for the primary cell and the neighbor cells so that the UE can receive requested MBMS data. The UE receives MBMS data transmitted from the respective cells at the same transmission time, and performs soft combining on the received MBMS data.

Abstract: Storage nodes for semiconductor memory devices may be fabricated by repeatedly forming conductive and insulating spacers on mold oxide layer pattern sidewalls, to thereby obtain fine line patterns which can increase the surface area of the storage node electrodes. Supporters also may be provided that are configured to support at least one freestanding storage node electrode, to thereby reduce or prevent the storage node electrode from falling or bending towards an adjacent storage node electrode.

Abstract: Storage nodes for semiconductor memory devices may be fabricated by repeatedly forming conductive and insulating spacers on mold oxide layer pattern sidewalls, to thereby obtain fine line patterns which can increase the surface area of the storage node electrodes. Supporters also may be provided that are configured to support at least one freestanding storage node electrode, to thereby reduce or prevent the storage node electrode from falling or bending towards an adjacent storage node electrode.

Abstract: A fabrication method for forming a semiconductor device having COB (capacitor-over-bit line) structure is provided. A lower insulating film is formed on a substrate. Bit line patterns are formed on a portion of the lower insulating film. Each of the bit line patterns comprises a conductive bit line, a lower capping strip and an upper capping strip, which are sequentially stacked. Mask-defining layer is formed on the other portion of the lower insulating film. The upper capping strips are removed by wet etching technique to form a recess region. The lower capping strips and a portion of the mask-defining layer is etched isotropically to enlarge the recess region. An insulating mask is formed in the enlarged recess region. BC (buried contact) holes are formed substantially in self-aligned manner to the bit lines by using the mask as an etch mask. According to the present invention, the unfavorable electrical contact between the storage electrodes and the bit lines can be significantly relieved.

Abstract: An integrated circuit transistor structure can include a gate electrode on a substrate and a source/drain region in the substrate adjacent to the gate electrode. An anti-punchthrough layer, separate from the substrate, is adjacent to the source/drain region.