Patents by Inventor C. Hunter
C. Hunter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20140183393Abstract: A gate valve for use in oil field applications and including a stem seal assembly. The stem seal assembly includes primary, secondary, and tertiary seals for sealing the space between the stem and the bonnet. The provision of multiple seals in the stem seal assembly provides redundancy that allows for maintenance of the seal between the components even if one or two of the individual seals fail.Type: ApplicationFiled: December 30, 2013Publication date: July 3, 2014Applicant: Vetco Gray Inc.Inventors: Rick C. Hunter, Jon B. Kahn, Fabio Okamoto Tanaka, Raul Vega
-
Publication number: 20140183392Abstract: A gate valve for use in oil field applications and including a stem seal assembly and a seat seal assembly. Each of the stem and seat seal assemblies accommodate independent primary, secondary, and tertiary seals for sealing the space between the stem and the bonnet, or the seat ring and the valve body, respectively. The provision of multiple seals in each assembly provides redundancy that allows for maintenance of the seal between the components even if one or two of the individual seals fail.Type: ApplicationFiled: December 30, 2013Publication date: July 3, 2014Applicant: Vetco Gray Inc.Inventors: Rick C. Hunter, Jon B. Kahn, Fabio Okamoto Tanaka
-
Publication number: 20140185398Abstract: A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant element. The method may further include using a latch to identify the redundant element. The method may also include that upon an event, using a value in the latch in an eFuse which subsequently selects the redundant element.Type: ApplicationFiled: March 4, 2013Publication date: July 3, 2014Applicant: International Business Machines CorporationInventors: Michele M. Franceschini, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano
-
Publication number: 20140183396Abstract: A gate valve for use in oil field applications and including a seat seal assembly. The seat seal assembly includes primary, secondary, and tertiary seals for sealing the space between the seat rings and the valve body. The provision of multiple seals in the seat seal assembly provides redundancy that allows for maintenance of the seal between the components even if one or two of the individual seals fail.Type: ApplicationFiled: December 30, 2013Publication date: July 3, 2014Applicant: Vetco Gray Inc.Inventors: Rick C. Hunter, Jon B. Kahn, Fabio Okamoto Tanaka
-
Publication number: 20140185397Abstract: A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant element. The method may further include using a latch to identify the redundant element. The method may also include that upon an event, using a value in the latch in an eFuse which subsequently selects the redundant element.Type: ApplicationFiled: January 2, 2013Publication date: July 3, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michele M. Franceschini, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano
-
Publication number: 20140164874Abstract: This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data.Type: ApplicationFiled: February 28, 2013Publication date: June 12, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Moinuddin K. Qureshi
-
Publication number: 20140164692Abstract: This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data.Type: ApplicationFiled: February 19, 2013Publication date: June 12, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Moinuddin K. Qureshi
-
Publication number: 20140164820Abstract: This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data.Type: ApplicationFiled: December 11, 2012Publication date: June 12, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Moinuddin K. Qureshi
-
Publication number: 20140164871Abstract: This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data.Type: ApplicationFiled: December 11, 2012Publication date: June 12, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Moinuddin K. Qureshi
-
Patent number: 8729045Abstract: The invention provides short interfering nucleic acids, either single-stranded or double-stranded, that cause RNAi-induced degradation of mRNA from the Nav1.8 sodium channel gene; to pharmaceutical compositions comprising such short interfering nucleic acids; recombinant vectors comprising such short interfering nucleic acids; a method for inhibiting translation of an mRNA; a method for inhibiting expression of a polypeptide; a method for blocking the membrane potential in a cell; a method for blocking the sodium current in a cell; and a method for inhibiting chronic pain.Type: GrantFiled: October 16, 2012Date of Patent: May 20, 2014Assignee: Merck Sharp & Dohme Corp. and Canji, Inc.Inventors: Sameer Goregaoker, John C. Hunter, Tony Priestley
-
Publication number: 20140115281Abstract: According to one embodiment a memory system includes a circuit card and a separable area array connector on the circuit card. The system also includes a memory device positioned on the circuit card, wherein the memory device is configured to communicate with a main processor of a computer system via the area array connector.Type: ApplicationFiled: October 22, 2012Publication date: April 24, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul W. Coteus, Shawn A. Hall, Hillery C. Hunter, Douglas J. Joseph, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Todd E. Takken
-
Patent number: 8705307Abstract: An embodiment provided is a memory system with dynamic refreshing that includes a memory device with memory cells. The system also includes a refresh module in communication with the memory device and with a memory controller, the refresh module configured for receiving a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is responsive to at least one of a desired bandwidth characteristic and a desired latency characteristic.Type: GrantFiled: November 17, 2011Date of Patent: April 22, 2014Assignee: International Business Machines CorporationInventors: Joab D. Henderson, Hillery C. Hunter, Warren E. Maule, Jeffrey A. Stuecheli
-
Patent number: 8691831Abstract: Disclosed are compounds of the formula I or a stereoisomer, tautomer, or pharmaceutically acceptable salt or solvate thereof, wherein each variable in Formula I are as defined in the specification; and pharmaceutical compositions comprising the compounds of formula I. Also disclosed are methods of inhibiting aspartyl protease, and in particular, the methods of treating cardiovascular diseases, cognitive and neurodegenerative diseases, and the methods of inhibiting of Human Immunodeficiency Virus, plasmepins, cathepsin D and protozoal enzymes. Also disclosed are methods of treating cognitive or neurodegenerative diseases using the compounds of formula I in combination with a cholinesterase inhibitor or a muscarinic m1 agonist or m2 antagonist.Type: GrantFiled: March 9, 2012Date of Patent: April 8, 2014Assignees: Merck Sharp & Dohme Corp., Pharmacopeia Drug Discovery, Inc.Inventors: Zhaoning Zhu, Brian McKittrick, Zhong-Yue Sun, Yuanzan C. Ye, Johannes H. Voight, Corey O. Strickland, Elizabeth M. Smith, Andrew W. Stamford, William J. Greenlee, Robert D. Mazzola, Jr., John P. Caldwell, Jared N. Cumming, Lingyan Wang, Yusheng Wu, Ulrich Iserloh, Xiaoxiang Liu, Tao Guo, Thuy X. E. Le, Kurt W. Saionz, Suresh D. Babu, Rachael C. Hunter, Michelle L. Morris, Huizhong Gu, Gang Qian, Dawit Tadesse, Ying Huang, Guoqing Li, Jianping Pan, Jeffrey A. Misiaszek, Gaifa Lai, Jingqi Duo, Chuanxing Qu, Yuefei Shao
-
Patent number: 8691833Abstract: Disclosed are compounds of the formula I or a stereoisomer, tautomer, or pharmaceutically acceptable salt or solvate thereof, wherein each variable in Formula 1 are as defined in the specification; and pharmaceutical compositions comprising the compounds of formula I. Also disclosed are methods of inhibiting aspartyl protease, and in particular, the methods of treating cardiovascular diseases, cognitive and neurodegenerative diseases, and the methods of inhibiting of Human Immunodeficiency Virus, plasmepins, cathepsin D and protozoal enzymes. Also disclosed are methods of treating cognitive or neurodegenerative diseases using the compounds of formula I in combination with a cholinesterase inhibitor or a muscarinic m1 agonist or m2 antagonist.Type: GrantFiled: March 8, 2012Date of Patent: April 8, 2014Assignees: Merck Sharp & Dohme Corp., Pharmacopeia Inc.Inventors: Zhaoning Zhu, Brian McKittrick, Zhong-Yue Sun, Yuanzan C. Ye, Johannes H. Voight, Corey O. Strickland, Elizabeth M. Smith, Andrew W. Stamford, William J. Greenlee, Robert D. Mazzola, Jr., John P. Caldwell, Jared N. Cumming, Lingyan Wang, Yusheng Wu, Ulrich Iserloh, Xiaoiang Liu, Tao Guo, Thuy X.E. Le, Kurt W. Saionz, Suresh D. Babu, Rachael C. Hunter, Michelle L. Morris, Huizhong Gu, Gang Qian, Dawit Tadesse, Ying Huang, Guoqing Li, Jianping Pan, Jeffrey A. Misiaszek, Gaifa Lai, Jingqi Duo, Chuanxing Qu, Yuefei Shao
-
Patent number: 8683128Abstract: A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory controller includes a physical read queue that buffers data read from the system memory via the memory bus and a physical write queue that buffers data to be written to the system memory via the memory bus. The memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory.Type: GrantFiled: May 7, 2010Date of Patent: March 25, 2014Assignee: International Business Machines CorporationInventors: David M. Daly, Benjiman L. Goodman, Hillery C. Hunter, William J. Starke, Jeffrey A. Stuecheli
-
Publication number: 20140057910Abstract: Disclosed are compounds of the formula I or a stereoisomer, tautomer, or pharmaceutically acceptable salt or solvate thereof, wherein W is a bond, —C(?S)—, —S(O)—, —S(O)2—, —C(?O)—, —O—, —C(R6)(R7)—, —N(R5)— or —C(?N(R5))—; X is —O—, —N(R5)— or —C(R6)(R7)—; provided that when X is —O—, U is not —O—, —S(O)—, —S(O)2—, —C(?O)— or —C(?NR5)—; U is a bond, —S(O)—, —S(O)2—, —C(O)—, —O—, —P(O)(OR15)—, —C(?NR5)—, —(C(R6)(R7))b— or —N(R5)—; wherein b is 1 or 2; provided that when W is —S(O)—, —S(O)2—, —O—, or —N(R5)—, U is not —S(O)—, —S(O)2—, —O—, or —N(R5)—; provided that when X is —N(R5)— and W is —S(O)—, —S(O)2—, —O—, or —N(R5)—, then U is not a bond; and R1, R2, R3, R4, R5, R6, and R7 are as defined in the specification; and pharmaceutical compositions comprising the compounds of formula I.Type: ApplicationFiled: February 22, 2012Publication date: February 27, 2014Applicant: Schering CorporationInventors: Zhaoning Zhu, Brian McKittrick, Zhong-Yue Sun, Yuanzan C. Ye, Johannes H. Voight, Corey Strickland, Elizabeth M. Smith, Andrew W. Stamford, William J. Greenlee, Robert Mazzola, John Caldwell, Jared N. Cumming, Lingyan Wang, Yusheng Wu, Ulrich Iserloh, Tao Guo, Thuy X.H. Le, Kurt W. Saionz, Suresh D. Babu, Rachael C. Hunter
-
Patent number: 8659959Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.Type: GrantFiled: August 6, 2012Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Kyu-Hyoun Kim, George L. Chiu, Paul W. Coteus, Daniel M. Dreps, Kevin C. Gower, Hillery C. Hunter, Charles A. Kilmer, Warren E. Maule
-
Patent number: 8645627Abstract: A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory controller includes a physical read queue that buffers data read from the system memory via the memory bus and a physical write queue that buffers data to be written to the system memory via the memory bus. The memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory.Type: GrantFiled: April 16, 2012Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: David M. Daly, Benjiman L. Goodman, Hillery C. Hunter, William J. Starke, Jeffrey A. Stuecheli
-
Patent number: 8635401Abstract: A method for performing refresh operations is disclosed. In response to a completion of a memory operation, a determination is made whether or not a refresh backlog count is greater than a first predetermined value. In a determination that the refresh backlog count is greater than the first predetermined value, a refresh operation is performed as soon as possible. In a determination that the refresh backlog count is not greater than the first predetermined value, a refresh operation is performed after a delay of an idle count value.Type: GrantFiled: April 23, 2012Date of Patent: January 21, 2014Assignee: International Business Machines CorporationInventors: John S. Dodson, Benjiman L. Goodman, Hillery C. Hunter, Steven Powell, Jeffrey A. Stuecheli
-
Patent number: 8622139Abstract: Wellhead-based systems, apparatus, and methods for controlling a well are provided. During a failure of an emergency system such as a blowout provider, a wellhead based emergency control apparatus according to an embodiment of the invention can be employed to control the well. A casing strings compression assembly can radially compress each of the casing strings and/or drilling pipe extending through the wellhead housing to restrict or stop well fluid passage. A casing strings penetrator of an emergency well fluid diversion assembly can also or alternatively be employed to form an aperture in the casing strings. A diverter, integral with or connected to the penetrator, is extended through an aperture in a side of the wellhead housing and one or more of the apertures cut by the penetrator to divert well fluid from within the wellhead housing through a passageway in the diverter and to an external conduit.Type: GrantFiled: December 15, 2010Date of Patent: January 7, 2014Assignee: Vetco Gray Inc.Inventors: Ryan R. Herbel, Rick C. Hunter