Patents by Inventor C. Hunter

C. Hunter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DRAM CONTROLLER FOR VARIABLE REFRESH OPERATION TIMING
    Publication number: 20150347036
    Abstract: A method for selection of a DRAM refresh timing in a DRAM memory system is disclosed. The method may include running a workload for a first number of refresh intervals using a first DRAM refresh timing and making a first workload throughput measurement for the first number of refresh intervals. The method may also include running the workload for a second number of refresh intervals using a second DRAM refresh timing and making a second workload throughput measurement for the second number of refresh intervals. The method may further include deciding if the first throughput measurement is greater than the second throughput measurement, and then selecting the first DRAM refresh timing as a selected DRAM refresh timing, or deciding if the second throughput measurement is greater than the first throughput measurement, then selecting the second DRAM refresh timing as the selected DRAM refresh timing.
    Type: Application
    Filed: August 11, 2015
    Publication date: December 3, 2015
    Inventors: Hillery C. Hunter, Kyu-hyoun Kim, Janani Mukundan
  • DRAM controller for variable refresh operation timing
    Patent number: 9196347
    Abstract: A method for selection of a DRAM refresh timing in a DRAM memory system is disclosed. The method may include running a workload for a first number of refresh intervals using a first DRAM refresh timing and making a first workload throughput measurement for the first number of refresh intervals. The method may also include running the workload for a second number of refresh intervals using a second DRAM refresh timing and making a second workload throughput measurement for the second number of refresh intervals. The method may further include deciding if the first throughput measurement is greater than the second throughput measurement, and then selecting the first DRAM refresh timing as a selected DRAM refresh timing, or deciding if the second throughput measurement is greater than the first throughput measurement, then selecting the second DRAM refresh timing as the selected DRAM refresh timing.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hillery C. Hunter, Kyu-hyoun Kim, Janani Mukundan
  • DATA RETRIEVAL FROM STACKED COMPUTER MEMORY
    Publication number: 20150331764
    Abstract: Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device. In response, the primary driver module is disabled and an emergency driver module is enabled. Each of the plurality of slave memory chips are selected using a multiplexing unit to retrieve data using the emergency driver module.
    Type: Application
    Filed: May 13, 2014
    Publication date: November 19, 2015
    Applicant: International Business Machines Corporation
    Inventors: Saurabh Chadha, Hillery C. Hunter, Kyu-hyoun Kim, Abhijit Saurabh, Saravanan Sethuraman, Kenneth L. Wright
  • DATA RETRIEVAL FROM STACKED COMPUTER MEMORY
    Publication number: 20150331768
    Abstract: Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device. In response, the primary driver module is disabled and an emergency driver module is enabled. Each of the plurality of slave memory chips are selected using a multiplexing unit to retrieve data using the emergency driver module.
    Type: Application
    Filed: August 19, 2014
    Publication date: November 19, 2015
    Inventors: Saurabh Chadha, Hillery C. Hunter, Kyu-hyoun Kim, Abhijit Saurabh, Saravanan Sethuraman, Kenneth L. Wright
  • Error-correcting code distribution for memory systems
    Patent number: 9189327
    Abstract: According to one embodiment, a memory system includes a plurality of memory devices and a memory controller operatively coupled to the memory devices. The memory controller is configured to partition write data into a plurality of data blocks, where each data block is associated with one of the memory devices. The memory controller is further configured to generate an instance of a local error-correcting code (ECC) corresponding to each data block, and merge each data block with the corresponding instance of the local ECC to form an encoded data block for each memory device. Additionally, the memory controller is configured to write each encoded data block to the memory devices such that each memory device stores one of the data blocks with the corresponding instance of the local ECC. A global ECC and a local ECC of the global ECC can also be included in the memory system.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: November 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Kenneth L. Wright
  • High temperature coating resistant to damage from decompression
    Patent number: 9163739
    Abstract: A coating for use in protecting surfaces susceptible to environmental degradation. The coating may be applied to metallic surfaces for providing a barrier against elements and/or ambient conditions that would otherwise degrade the surface material. The coating includes multiple layers, where a thermoplastic polymer is included, wholly or partly, within one or more of the layers. Example applications of the coating are for protecting valve seat seals and valve stem seals of a valve assembly used in conjunction with handling of fluids produced from a subterranean formation.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: October 20, 2015
    Assignee: Vetco Gray Inc.
    Inventors: Rick C. Hunter, Khanh Anh Duong
  • Securing the contents of a memory device
    Patent number: 9146883
    Abstract: A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable. The quick erase capability may allow use of the memory device for new write operations and for reading the newly written data immediately once the erase command is received and executed. The quick erase capability may begin a physical erase process of data not newly written without altering other aspects of the quick erase. Aspects may be accomplished with one or more bits per row in a memory device.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: September 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Warren E. Maule
  • Securing the contents of a memory device
    Patent number: 9146882
    Abstract: A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable. The quick erase capability may allow use of the memory device for new write operations and for reading the newly written data immediately once the erase command is received and executed. The quick erase capability may begin a physical erase process of data not newly written without altering other aspects of the quick erase. Aspects may be accomplished with one or more bits per row in a memory device.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: September 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Warren E. Maule
  • Valve Vented Redundant Stem Seal System
    Publication number: 20150226338
    Abstract: A valve stem packing assembly can seal a valve stem to a valve body having a body cavity. The packing assembly includes a packing ring circumscribing the valve stem within a stem opening extending axially through the valve body. A primary dynamic seal is positioned to seal a dynamic leak path between the packing ring and the valve stem. A secondary dynamic seal is spaced axially apart and functionally independent from the primary dynamic seal and positioned to redundantly seal the dynamic leak path. A primary static seal is positioned to seal a static leak path between the packing ring and the valve body. A secondary static seal is spaced axially apart and functionally independent from the primary static seal and positioned to redundantly seal the static leak path.
    Type: Application
    Filed: April 20, 2015
    Publication date: August 13, 2015
    Applicant: Vetco Gray Inc.
    Inventor: Rick C. Hunter
  • ERROR FEEDBACK AND LOGGING WITH MEMORY ON-CHIP ERROR CHECKING AND CORRECTING (ECC)
    Publication number: 20150212886
    Abstract: Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency.
    Type: Application
    Filed: June 30, 2014
    Publication date: July 30, 2015
    Inventors: Paul W. Coteus, Hillery C. Hunter, Charles Arthur Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Warren E. Maule, Vipinchandra Patel
  • ERROR FEEDBACK AND LOGGING WITH MEMORY ON-CHIP ERROR CHECKING AND CORRECTING (ECC)
    Publication number: 20150212885
    Abstract: Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency.
    Type: Application
    Filed: January 30, 2014
    Publication date: July 30, 2015
    Applicant: International Business Machines Corporation
    Inventors: Paul W. Coteus, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Warren E. Maule, Vipinchandra Patel
  • DYNAMIC TEMPERATURE ADJUSTMENTS IN SPIN TRANSFER TORQUE MAGNETORESISTIVE RANDOM-ACCESS MEMORY (STT-MRAM)
    Publication number: 20150206567
    Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method of managing memory includes determining a temperature associated with the memory and determining a level of write queue utilization associated with the memory. A write operation may be performed based on the level of write queue utilization and the temperature.
    Type: Application
    Filed: January 21, 2014
    Publication date: July 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers, Vijayalakshmi Srinivasan
  • DYNAMIC TEMPERATURE ADJUSTMENTS IN SPIN TRANSFER TORQUE MAGNETORESISTIVE RANDOM-ACCESS MEMORY (STT-MRAM)
    Publication number: 20150206569
    Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method of managing memory includes determining a temperature associated with the memory and determining a level of write queue utilization associated with the memory. A write operation may be performed based on the level of write queue utilization and the temperature.
    Type: Application
    Filed: June 30, 2014
    Publication date: July 23, 2015
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers, Vijayalakshmi Srinivasan
  • DETERMINING AND STORING BIT ERROR RATE RELATIONSHIPS IN SPIN TRANSFER TORQUE MAGNETORESISTIVE RANDOM-ACCESS MEMORY (STT-MRAM)
    Publication number: 20150206566
    Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method may include determining a performance characteristic using relationship information that relates a bit error rate to at least one of a programming pulse width, a temperature, a history-based predictive performance parameter , a coding scheme, and a voltage level also associated with a memory. The performance characteristic is stored and used to manage a write operation associated with the memory.
    Type: Application
    Filed: January 21, 2014
    Publication date: July 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers, Vijayalakshmi Srinivasan
  • DETERMINING AND STORING BIT ERROR RATE RELATIONSHIPS IN SPIN TRANSFER TORQUE MAGNETORESISTIVE RANDOM-ACCESS MEMORY (STT-MRAM)
    Publication number: 20150206568
    Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method may include determining a performance characteristic using relationship information that relates a bit error rate to at least one of a programming pulse width, a temperature, a history-based predictive performance parameter , a coding scheme, and a voltage level also associated with a memory. The performance characteristic is stored and used to manage a write operation associated with the memory.
    Type: Application
    Filed: June 30, 2014
    Publication date: July 23, 2015
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers, Vijayalakshmi Srinivasan
  • DRAM error detection, evaluation, and correction
    Patent number: 9087612
    Abstract: Errors on a dynamic random access memory (“DRAM”) having an error correcting decoder (“ECC”) can be detected by the ECC when reading a row of the DRAM. The ECC includes error correcting code logic. If errors are detected that cannot be corrected by the ECC logic, test control logic determines weak cell information for the row, evaluates the errors using the weak cell information, and may correct the errors. The weak cell information may include weak cell locations and failure values.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Moinuddin K. Qureshi
  • Implementing memory device with sub-bank architecture
    Patent number: 9064602
    Abstract: A method, system and memory controller are provided for implementing memory devices with sub-bank architecture in a computer system. An array is divided into sub-blocks having odd bit lines and even bit lines. The sub-blocks are alternated with rows of sense amplifiers; wherein a particular row of sense amplifiers connects only to odd bit lines and a next row of sense amplifiers connects only to even bit lines. More than one word line for a sub-block is allowed to be active at the same time, where a first active word line will select memory cells connected to even bit lines and a second active word line will select memory cells connected to odd bit lines.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: June 23, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule
  • ERROR-CORRECTING CODE DISTRIBUTION FOR MEMORY SYSTEMS
    Publication number: 20150143201
    Abstract: According to one embodiment, a memory system includes a plurality of memory devices and a memory controller operatively coupled to the memory devices. The memory controller is configured to partition write data into a plurality of data blocks, where each data block is associated with one of the memory devices. The memory controller is further configured to generate an instance of a local error-correcting code (ECC) corresponding to each data block, and merge each data block with the corresponding instance of the local ECC to form an encoded data block for each memory device. Additionally, the memory controller is configured to write each encoded data block to the memory devices such that each memory device stores one of the data blocks with the corresponding instance of the local ECC. A global ECC and a local ECC of the global ECC can also be included in the memory system.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 21, 2015
    Applicant: International Business Machines Corporation
    Inventors: Paul W. Coteus, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Kenneth L. Wright
  • Managing errors in a DRAM by weak cell encoding
    Patent number: 9037930
    Abstract: This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Moinuddin K. Qureshi
  • IMPLEMENTING MEMORY DEVICE WITH SUB-BANK ARCHITECTURE
    Publication number: 20150109874
    Abstract: A method, system and memory controller are provided for implementing memory devices with sub-bank architecture in a computer system. An array is divided into sub-blocks having odd bit lines and even bit lines. The sub-blocks are alternated with rows of sense amplifiers; wherein a particular row of sense amplifiers connects only to odd bit lines and a next row of sense amplifiers connects only to even bit lines. More than one word line for a sub-block is allowed to be active at the same time, where a first active word line will select memory cells connected to even bit lines and a second active word line will select memory cells connected to odd bit lines.
    Type: Application
    Filed: October 23, 2013
    Publication date: April 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule