Abstract: A wellhead assembly includes a wellhead housing with a bore and an annular lock groove on an inner diameter surface of the bore. A wellbore member is concentrically located within the bore of the wellhead housing, defining an annulus between the wellbore member and the wellhead housing. An annular lock ring is positioned in the annulus. The annular lock ring has an outer diameter profile for engaging the lock groove and is radially expandable from an unset position to a set position. An energizing ring is positioned in the annulus to push the lock ring outward to the set position as the energizing ring moves downward. A retainer selectively engages the energizing ring and limits axial upward movement of the energizing ring relative to the wellbore member, retains the annular lock in the set position, and prevents axial upward movement of the wellbore member relative to the wellhead housing.

Abstract: An aspect includes determining a configuration change to at least one memory device of a memory system. A band switch enable command is sent from a memory controller to the at least one memory device indicating the configuration change. One or more internal circuits of the at least one memory device are set into a quiescent mode based on receiving the band enable command. One or more of a voltage and a frequency of the at least one memory device are adjusted to implement the configuration change. A band switch disable command is sent from the memory controller to the at least one memory device based on completing the adjusting. The one or more internal circuits are enabled to operate using the adjustment based on receiving the band switch disable command from the memory controller.

Abstract: A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ECC) bits and an extended correction table. The extended correction table stores error information additional to the ECC bits for one or more of the data in the memory array. The system also includes a controller to control the memory device to write and read the data.

Abstract: A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ECC) bits and an extended correction table. The extended correction table stores error information additional to the ECC bits for one or more of the data in the memory array. The system also includes a controller to control the memory device to write and read the data.

Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.

Abstract: A valve stem packing assembly can seal a valve stem to a valve body having a body cavity. The packing assembly includes a packing ring circumscribing the valve stem within a stem opening extending axially through the valve body. A primary dynamic seal is positioned to seal a dynamic leak path between the packing ring and the valve stem. A secondary dynamic seal is spaced axially apart and functionally independent from the primary dynamic seal and positioned to redundantly seal the dynamic leak path. A primary static seal is positioned to seal a static leak path between the packing ring and the valve body. A secondary static seal is spaced axially apart and functionally independent from the primary static seal and positioned to redundantly seal the static leak path.

Abstract: Examples of techniques for a built-in self-test (BIST) for embedded spin-transfer torque magnetic random access memory (STT-MRAM) are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: initiating, by a processor, a BIST for the STT-MRAM; performing, by the processor, an error-correcting code (ECC) test for a portion of the STT-MRAM; responsive to the ECC test not being passed, determining whether a maximum signal is reached; responsive to the maximum signal not being reached, increasing the signal and performing the ECC test again; and responsive to the maximum signal being reached, determining that the portion of the STT-MRAM is bad.

Abstract: A wellhead housing has a bore with an inner seal surface. A hanger with an outer seal surface lands in the bore. Wickers are formed on at least one of the seal surfaces. A metal seal ring lands between the seal surfaces, the seal ring having annular inner and outer legs separated by an annular slot. An energizing ring has inner and outer diameter surfaces that slide against the inner and outer legs of the seal ring when the energizing ring is moved downward in the slot to radially deform the inner and outer legs into sealing engagement with the wellhead housing and hanger. The energizing ring has an inner diameter relief and an outer diameter relief, each being a partially circumferential groove extending upward from a lower rim. The reliefs define a bridge of narrower radial thickness in the lower rim.

Abstract: A droplet delivery device and related methods for delivering precise and repeatable dosages to a subject for pulmonary use is disclosed. The droplet delivery device includes a housing, a reservoir, and ejector mechanism, and at least one differential pressure sensor. The droplet delivery device is automatically breath actuated by the user when the differential pressure sensor senses a predetermined pressure change within housing. The droplet delivery device is then actuated to generate a stream of droplets having an average ejected droplet diameter within the respirable size range, e.g, less than about 5 ?m, so as to target the pulmonary system of the user.

Abstract: A droplet delivery device and related methods for delivering precise and repeatable dosages to a subject for pulmonary use is disclosed. The droplet delivery device includes a housing, a reservoir, and ejector mechanism, and at least one differential pressure sensor. The droplet delivery device is automatically breath actuated by the user when the differential pressure sensor senses a predetermined pressure change within housing. The droplet delivery device is then actuated to generate a stream of droplets having an average ejected droplet diameter within the respirable size range, e.g, less than about 5 ?m, so as to target the pulmonary system of the user.

Abstract: Embodiments of the present disclosure provide a method, computer program product, and system for monitoring a dynamic random-access memory (DRAM) device to detect and respond to a cryogenic attack. A processor receives a set of memory information about a DRAM device. The processor then determines a set of error indicators by processing the memory information using a set of decision parameters. The error indicators are then compared to an attack syndrome to determine if the DRAM is experiencing a cryogenic attack. If the DRAM is experiencing a cryogenic attack, access to the DRAM device is disabled.

Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.

Abstract: Provided herein are methods and systems for interfering with viability of bacteria and related compounds and compositions.

Abstract: An aspect includes determining a configuration change to at least one memory device of a memory system. A band switch enable command is sent from a memory controller to the at least one memory device indicating the configuration change. One or more internal circuits of the at least one memory device are set into a quiescent mode based on receiving the band enable command. One or more of a voltage and a frequency of the at least one memory device are adjusted to implement the configuration change. A band switch disable command is sent from the memory controller to the at least one memory device based on completing the adjusting. The one or more internal circuits are enabled to operate using the adjustment based on receiving the band switch disable command from the memory controller.

Abstract: According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition, where the write-back indicator is a discrete signal sent to a memory controller, and the at least one non-volatile memory device asserting the write-back indicator extends cycle timing monitored by the memory controller while the write-back indicator is asserted. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator.

Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.

Abstract: A flash translation layer method, system, and computer program product, include sending a request with a type of feature and a flash characteristic of a translation table for a Solid-State disk, receiving, via a meta-flash translation layer (meta-FTL), the request and checking for a number of free blocks in a NAND chip, and instantiating a range in the NAND chip including the number of free blocks using the meta-FTL to create a compatible range of blocks for the type of feature and the flash characteristic of the translation table if the checking returns a confirmation that the number of free blocks is available.

Abstract: A gate valve for use in oil field applications and including a seat seal assembly. The seat seal assembly includes primary, secondary, and tertiary seals for sealing the space between the seat rings and the valve body. The provision of multiple seals in the seat seal assembly provides redundancy that allows for maintenance of the seal between the components even if one or two of the individual seals fail.

Abstract: An aspect includes determining a configuration change to at least one memory device of a memory system. A band switch enable command is sent from a memory controller to the at least one memory device indicating the configuration change. One or more internal circuits of the at least one memory device are set into a quiescent mode based on receiving the band enable command. One or more of a voltage and a frequency of the at least one memory device are adjusted to implement the configuration change. A band switch disable command is sent from the memory controller to the at least one memory device based on completing the adjusting. The one or more internal circuits are enabled to operate using the adjustment based on receiving the band switch disable command from the memory controller.

Abstract: A system and methods controlling wake events in a data processing system is described. A broadcast wake-up signal staggering order is determined in response to a first wake event. A staggered broadcast wake-up signal is distributed to a plurality of processing elements based on the broadcast wake-up signal staggering order. The broadcast wake-up signal staggering order is changed in response to a second wake event. And a changed staggered broadcast wake-up signal is distributed to a plurality of processing elements based on the changed broadcast wake-up signal staggering order.