Patents by Inventor C. Hunter

C. Hunter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9880896
    Abstract: Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: January 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul W. Coteus, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Warren E. Maule, Vipinchandra Patel
  • Publication number: 20170319796
    Abstract: A droplet delivery device and related methods for delivering precise and repeatable dosages to a subject for pulmonary use is disclosed. The droplet delivery device includes a housing, a reservoir, and ejector mechanism, and at least one differential pressure sensor. The droplet delivery device is automatically breath actuated by the user when the differential pressure sensor senses a predetermined pressure change within housing. The droplet delivery device is then actuated to generate a stream of droplets having an average ejected droplet diameter within the respirable size range, e.g, less than about 5 ?m, so as to target the pulmonary system of the user.
    Type: Application
    Filed: May 16, 2017
    Publication date: November 9, 2017
    Applicant: PNEUMA RESPIRATORY, INC.
    Inventors: Louis Thomas Germinario, John H. Hebrank, Charles Eric Hunter, Jack C. Hunter, Chengjie Li, Christopher W. Maurer
  • Publication number: 20170319797
    Abstract: A droplet delivery device and related methods for delivering precise and repeatable dosages to a subject for pulmonary use is disclosed. The droplet delivery device includes a housing, a reservoir, and ejector mechanism, and at least one differential pressure sensor. The droplet delivery device is automatically breath actuated by the user when the differential pressure sensor senses a predetermined pressure change within housing. The droplet delivery device is then actuated to generate a stream of droplets having an average ejected droplet diameter within the respirable size range, e.g, less than about 5 ?m, so as to target the pulmonary system of the user.
    Type: Application
    Filed: May 16, 2017
    Publication date: November 9, 2017
    Applicant: PNEUMA RESPIRATORY, INC.
    Inventors: Louis Thomas Germinario, John H. Hebrank, Charles Eric Hunter, Jack C. Hunter, Chengjie Li, Christopher W. Maurer
  • Publication number: 20170317055
    Abstract: Examples of techniques for an integrated wafer-level processing system are disclosed. In one example implementation according to aspects of the present disclosure, an integrated wafer-level processing system includes a memory wafer and a processing element connected to the memory wafer via a data connection.
    Type: Application
    Filed: May 2, 2016
    Publication date: November 2, 2017
    Inventors: Philip G. Emma, Hillery C. Hunter, John U. Knickerbocker
  • Publication number: 20170284165
    Abstract: A wellhead housing has a bore with an inner seal surface. A hanger with an outer seal surface lands in the bore. Wickers are formed on at least one of the seal surfaces. A metal seal ring lands between the seal surfaces, the seal ring having annular inner and outer legs separated by an annular slot. An energizing ring has inner and outer diameter surfaces that slide against the inner and outer legs of the seal ring when the energizing ring is moved downward in the slot to radially deform the inner and outer legs into sealing engagement with the wellhead housing and hanger. The energizing ring has an inner diameter relief and an outer diameter relief, each being a partially circumferential groove extending upward from a lower rim. The reliefs define a bridge of narrower radial thickness in the lower rim.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Inventors: Joseph W. Pallini, Rick C. Hunter, David L. Ford, Robert Jen-Yue Du
  • Publication number: 20170283763
    Abstract: Provided herein are methods and systems for interfering with viability of bacteria and related compounds and compositions.
    Type: Application
    Filed: January 30, 2017
    Publication date: October 5, 2017
    Inventors: Dianne K. NEWMAN, Ryan C. HUNTER
  • Patent number: 9761294
    Abstract: A method for operating a memory system comprises receiving a write request associate with data, decoding an address of the write request, receiving thermal data indicating a temperature at the address of the write request, determining whether the temperature is above a threshold temperature, and writing the data to the address responsive to determining that the temperature is not above the threshold temperature.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: September 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael B. Healy, Hillery C. Hunter, Saravanan Sethuraman
  • Patent number: 9759334
    Abstract: A gate valve for use in oil field applications and including a stem seal assembly and a seat seal assembly. Each of the stem and seat seal assemblies accommodate independent primary, secondary, and tertiary seals for sealing the space between the stem and the bonnet, or the seat ring and the valve body, respectively. The provision of multiple seals in each assembly provides redundancy that allows for maintenance of the seal between the components even if one or two of the individual seals fail.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: September 12, 2017
    Assignee: Vetco Gray Inc.
    Inventors: Rick C. Hunter, Jon B. Kahn, Fabio Okamoto Tanaka
  • Patent number: 9760504
    Abstract: Keys are generated at a memory device with a period of time elapsing between generation of each key. A request is received from a memory controller for the most recently generated key. The memory device communicates the first key to the memory controller. Access to nonvolatile memory on the memory device is locked. An unlock command with a second key is received from the memory controller. The memory device determines that the second key matches the first key and unlocks access to the nonvolatile memory in response.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Stephen P. Glancy, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Vipin Patel
  • Patent number: 9747148
    Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: August 29, 2017
    Assignee: International Business Machines Corporation
    Inventors: Michael B. Healy, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule
  • Patent number: 9740496
    Abstract: A processor and a method implemented by the processor to obtain computation results are described. The processor includes a unified reuse table embedded in a processor pipeline, the unified reuse table including a plurality of entries, each entry of the plurality of entries corresponding with a computation instruction or a set of computation instructions. The processor also includes a functional unit to perform a computation based on a corresponding instruction.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers, Vijayalakshmi Srinivasan
  • Patent number: 9740497
    Abstract: A processor and a method implemented by the processor to obtain computation results are described. The processor includes a unified reuse table embedded in a processor pipeline, the unified reuse table including a plurality of entries, each entry of the plurality of entries corresponding with a computation instruction or a set of computation instructions. The processor also includes a functional unit to perform a computation based on a corresponding instruction.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers, Vijayalakshmi Srinivasan
  • Publication number: 20170235632
    Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.
    Type: Application
    Filed: May 1, 2017
    Publication date: August 17, 2017
    Inventors: Michael B. Healy, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule
  • Patent number: 9734008
    Abstract: A memory management system and method of managing output data resulting from a memory device storing raw data and error correction coding (ECC) bits are described. The system includes a controller to receive a read command and control a memory device based on the read command, the memory device to store raw data and error correction coding (ECC) bits and output the raw data and the ECC bits corresponding with memory addresses specified in the read command, and an ECC decoder to output an error vector associated with the memory addresses based on the raw data and the ECC bits corresponding with the memory addresses output by the memory device, the error vector associated with the memory addresses indicating errors in the raw data corresponding with the memory addresses. The system also includes a multiplexer (MUX) to output the error vector based on a selection indicated in the read command.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael B. Healy, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule
  • Patent number: 9733870
    Abstract: A memory management system and method of managing output data resulting from a memory device storing raw data and error correction coding (ECC) bits are described. The system includes a controller to receive a read command and control a memory device based on the read command, the memory device to store raw data and error correction coding (ECC) bits and output the raw data and the ECC bits corresponding with memory addresses specified in the read command, and an ECC decoder to output an error vector associated with the memory addresses based on the raw data and the ECC bits corresponding with the memory addresses output by the memory device, the error vector associated with the memory addresses indicating errors in the raw data corresponding with the memory addresses. The system also includes a multiplexer (MUX) to output the error vector based on a selection indicated in the read command.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael B. Healy, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule
  • Patent number: 9734885
    Abstract: A method for operating a memory system includes receiving thermal data indicating a temperature at addresses in a memory array, and a write request associate with data. An address of the write request is decoded. It is determined whether a temperature at the address of the write request is above a threshold temperature. The data is sent to a short latency write queue responsive to determining that the temperature is not above the threshold temperature.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael B. Healy, Hillery C. Hunter, Saravanan Sethuraman
  • Patent number: 9734095
    Abstract: Keys are generated at a memory device with a period of time elapsing between generation of each key. A request is received from a memory controller for the most recently generated key. The memory device communicates the first key to the memory controller. Access to nonvolatile memory on the memory device is locked. An unlock command with a second key is received from the memory controller. The memory device determines that the second key matches the first key and unlocks access to the nonvolatile memory in response.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Stephen P. Glancy, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Vipin Patel
  • Publication number: 20170228186
    Abstract: An aspect includes determining a configuration change to at least one memory device of a memory system. A band switch enable command is sent from a memory controller to the at least one memory device indicating the configuration change. One or more internal circuits of the at least one memory device are set into a quiescent mode based on receiving the band enable command. One or more of a voltage and a frequency of the at least one memory device are adjusted to implement the configuration change. A band switch disable command is sent from the memory controller to the at least one memory device based on completing the adjusting. The one or more internal circuits are enabled to operate using the adjustment based on receiving the band switch disable command from the memory controller.
    Type: Application
    Filed: February 5, 2016
    Publication date: August 10, 2017
    Inventors: Michael B. Healy, Hillery C. Hunter, Kyu-hyoun Kim
  • Patent number: 9690649
    Abstract: Classifying memory errors may include accessing data from a location within a memory array of a memory device. The memory array may include at least one bit field to store memory error classification information. One or more memory errors in the data may be determined. One or more memory errors may further be classified. In response to the classifying, memory error classification information may be stored as one or more bit values within the bit field.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: June 27, 2017
    Assignee: International Business Machines Corporation
    Inventors: Michael B. Healy, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule
  • Patent number: 9684555
    Abstract: A correctable memory error may be identified at a first address within a memory device. Based on at least the identifying, a first correctable memory error count may be updated from a first quantity to a second quantity. The second quantity may be determined to exceed or not exceed a threshold. In response to the determining, the first correctable memory error count of the second quantity may be: converted to a third quantity and reported to a host device accordingly, reported to a host device, or not reported to a host device.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventors: Michael B. Healy, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule