Patents by Inventor C. Kahn

C. Kahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11044196
    Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A multi-protocol I/O interconnect may include a switching fabric operatively coupled to a first protocol-specific controller and a second protocol-specific controller, and may be configured to simultaneously route packets of the first protocol to the first protocol-specific controller and packets of the second protocol to the second protocol-specific controller. Other embodiments may be described and claimed.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: June 22, 2021
    Assignee: Intel Corporation
    Inventors: Prashant R. Chandra, Kevin C. Kahn
  • Patent number: 10759428
    Abstract: A vehicle includes one or more laser scanners and an on-board vehicle computer system communicatively coupled to the laser scanners. The computer system uses information (e.g., coordinate points) obtained from the laser scanners to calculate a trailer angle (e.g., a cab-trailer angle) for the vehicle. The computer system may include a shape detection module that detects a trailer based on the information obtained from the laser scanners and an angle detection module that calculates an angle of the detected trailer relative to a laser scanner, calculates the orientation of the detected trailer based on that angle and dimensions (e.g., width and length) of the trailer, and calculates a cab-trailer angle based on the orientation of the trailer. The computer system may include an autonomous operation module configured to use the cab-trailer angle in an autonomous or computer-guided vehicle maneuver, such as a parking maneuver or backing maneuver.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: September 1, 2020
    Assignee: PACCAR INC
    Inventors: William C. Kahn, A. Brent Hankins
  • Patent number: 10324723
    Abstract: Disclosed is a digital processor comprising an instruction memory having a first input, a second input, a first output, and a second output. A program counter register is in communication with the first input of the instruction memory. The program counter register is configured to store an address of an instruction to be fetched. A data pointer register is in communication with the second input of the instruction memory. The data pointer register is configured to store an address of a data value in the instruction memory. An instruction buffer is in communication with the first output of the instruction memory. The instruction buffer is arranged to receive an instruction according to a value at the program counter register. A data buffer is in communication with the second output of the instruction memory. The data buffer is arranged to receive a data value according to a value at the data pointer register.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: June 18, 2019
    Assignee: NXP USA, Inc.
    Inventors: Peter J Wilson, Brian C Kahne, Jeffrey W Scott
  • Publication number: 20190166046
    Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A multi-protocol I/O interconnect may include a switching fabric operatively coupled to a first protocol-specific controller and a second protocol-specific controller, and may be configured to simultaneously route packets of the first protocol to the first protocol-specific controller and packets of the second protocol to the second protocol-specific controller. Other embodiments may be described and claimed.
    Type: Application
    Filed: September 21, 2018
    Publication date: May 30, 2019
    Inventors: Prashant R. CHANDRA, Kevin C. KAHN
  • Patent number: 10235225
    Abstract: A method of handling requests between contexts in a processing system includes, in a current context of a source processing system element (PSE): executing a send-and rendezvous instruction that specifies a destination PSE, a queue address in the destination PSE, a set of source registers, and a set of receive registers; and sending a send-and-rendezvous message (SRM) to the destination PSE, wherein the SRM includes an address of the destination PSE, a destination queue address, a source PSE address, and an identifier of the current context in the source PSE.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: March 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Peter J. Wilson, Brian C. Kahne
  • Patent number: 10110480
    Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A multi-protocol I/O interconnect may include a switching fabric operatively coupled to a first protocol-specific controller and a second protocol-specific controller, and may be configured to simultaneously route packets of the first protocol to the first protocol-specific controller and packets of the second protocol to the second protocol-specific controller. Other embodiments may be described and claimed.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Prashant R. Chandra, Kevin C. Kahn
  • Patent number: 10031753
    Abstract: In a pipelined element configured to execute multiple contexts and including an instruction pipeline and a plurality of context modules each having a register file and a functional unit, a method includes scheduling a first context for execution in the instruction pipeline. The instruction pipeline includes an execution unit having a plurality of functional units. Each functional unit of the plurality of functional units is configured to execute instructions of a scheduled context of the plurality of contexts. A first instruction of the first context which precedes an instruction loop of the first context is executed. In response to executing the first instruction, the first context is released from being scheduled for execution in the instruction pipeline and execution of the first context is continued using a first context module. The first context module includes a context-specific functional unit configured to execute the instruction loop.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: July 24, 2018
    Assignee: NXP USA, Inc.
    Inventors: Peter J Wilson, Brian C Kahne
  • Patent number: 9898386
    Abstract: An approach is provided in which an endianness violation detection sub-system detects endianness violations between hardware units. The endianness violation detection sub-system tracks memory operations performed by multiple hardware units via debug channels and generates lookup table entries that are stored in a lookup table. When the endianness violation detection sub-system detects endianness relevant load attributes of a load operation that are different than corresponding endianness relevant store attributes of a store operation, the endianness violation detection sub-system generates an endianness violation. In one embodiment, the endianness violation detection sub-system identifies an endianness violation when the endianness violation detection sub-system detects a difference in the byte ordering type between a hardware unit performing a store operation and a hardware unit performing a load operation.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: February 20, 2018
    Assignee: NXP USA, INC.
    Inventors: Brian C. Kahne, John H. Arends, Richard G. Collins, James C. Holt
  • Publication number: 20170361844
    Abstract: A vehicle includes one or more laser scanners and an on-board vehicle computer system communicatively coupled to the laser scanners. The computer system uses information (e.g., coordinate points) obtained from the laser scanners to calculate a trailer angle (e.g., a cab-trailer angle) for the vehicle. The computer system may include a shape detection module that detects a trailer based on the information obtained from the laser scanners and an angle detection module that calculates an angle of the detected trailer relative to a laser scanner, calculates the orientation of the detected trailer based on that angle and dimensions (e.g., width and length) of the trailer, and calculates a cab-trailer angle based on the orientation of the trailer. The computer system may include an autonomous operation module configured to use the cab-trailer angle in an autonomous or computer-guided vehicle maneuver, such as a parking maneuver or backing maneuver.
    Type: Application
    Filed: September 1, 2017
    Publication date: December 21, 2017
    Applicant: PACCAR Inc
    Inventors: William C. Kahn, A. Brent Hankins
  • Patent number: 9753790
    Abstract: A method of handling requests between contexts in a processing system includes, in a current context of a source processing system element (PSE): executing a send-and rendezvous instruction that specifies a destination PSE, a queue address in the destination PSE, a set of source registers, and a set of receive registers; and sending a send-and-rendezvous message (SRM) to the destination PSE, wherein the SRM includes an address of the destination PSE, a destination queue address, a source PSE address, and an identifier of the current context in the source PSE.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: September 5, 2017
    Assignee: NXP USA, Inc.
    Inventors: Peter J. Wilson, Brian C. Kahne
  • Publication number: 20170126553
    Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A multi-protocol I/O interconnect may include a switching fabric operatively coupled to a first protocol-specific controller and a second protocol-specific controller, and may be configured to simultaneously route packets of the first protocol to the first protocol-specific controller and packets of the second protocol to the second protocol-specific controller. Other embodiments may be described and claimed.
    Type: Application
    Filed: January 17, 2017
    Publication date: May 4, 2017
    Inventors: Prashant R. CHANDRA, Kevin C. KAHN
  • Patent number: 9582320
    Abstract: A processing system includes a processor configured to execute a plurality of instructions corresponding to a task, wherein the plurality of instructions comprises a resource transfer instruction to indicate a transfer of processing operations of the task from the processor to a different resource and a hint instruction which precedes the resource transfer instruction by a set of instructions within the plurality of instructions. A processor task scheduler is configured to schedule tasks to the processor, wherein, in response to execution of the hint instruction of the task, the processor task scheduler finalizes selection of a next task and loads a context of the selected next task into a background register file. The loading occurs concurrently with execution of the set of instructions between the hint instruction and resource transfer instruction, and, after loading is completed, the processor switches to the selected task in response to the resource transfer instruction.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 28, 2017
    Assignee: NXP USA, Inc.
    Inventors: James C. Holt, Brian C. Kahne, William C. Moyer
  • Patent number: 9565132
    Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A multi-protocol I/O interconnect may include a switching fabric operatively coupled to a first protocol-specific controller and a second protocol-specific controller, and may be configured to simultaneously route packets of the first protocol to the first protocol-specific controller and packets of the second protocol to the second protocol-specific controller. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: February 7, 2017
    Assignee: INTEL CORPORATION
    Inventors: Prashant R. Chandra, Kevin C. Kahn
  • Publication number: 20160379422
    Abstract: A display system suitable for use in a vehicle is set forth. The display system comprises a smart device, such as a cellular phone, tablet, smart display or the like, that is configured to display one or more types of vehicle information while at the same time diminishing any visual impairment caused by the device to the driver.
    Type: Application
    Filed: June 26, 2015
    Publication date: December 29, 2016
    Applicant: PACCAR Inc
    Inventor: William C. Kahn
  • Publication number: 20160368336
    Abstract: A vehicle includes one or more laser scanners and an on-board vehicle computer system communicatively coupled to the laser scanners. The computer system uses information (e.g., coordinate points) obtained from the laser scanners to calculate a trailer angle (e.g., a cab-trailer angle) for the vehicle. The computer system may include a shape detection module that detects a trailer based on the information obtained from the laser scanners and an angle detection module that calculates an angle of the detected trailer relative to a laser scanner, calculates the orientation of the detected trailer based on that angle and dimensions (e.g., width and length) of the trailer, and calculates a cab-trailer angle based on the orientation of the trailer. The computer system may include an autonomous operation module configured to use the cab-trailer angle in an autonomous or computer-guided vehicle maneuver, such as a parking maneuver or backing maneuver.
    Type: Application
    Filed: June 19, 2015
    Publication date: December 22, 2016
    Applicant: PACCAR INC
    Inventors: William C. Kahn, A. Brent Hankins
  • Patent number: 9507654
    Abstract: A processing system includes a first processing system element, and a second processing system element configured to communicate with the first processing system. The second processing system element includes a set of messaging queues. Each of the messaging queues includes one or more entries for storing data, a set of delegate queue addresses associated with one of the set of messaging queues; and a delegate queue associated with the set of messaging queues. The delegate queue includes a set of entries corresponding to the delegate queue addresses, and each of the entries of the delegate queue indicates whether a corresponding one of the set of messaging queues is storing data.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: November 29, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Peter J. Wilson, Brian C. Kahne
  • Publication number: 20160314030
    Abstract: A processing system includes a first processing system element, and a second processing system element configured to communicate with the first processing system. The second processing system element includes a set of messaging queues. Each of the messaging queues includes one or more entries for storing data, a set of delegate queue addresses associated with one of the set of messaging queues; and a delegate queue associated with the set of messaging queues. The delegate queue includes a set of entries corresponding to the delegate queue addresses, and each of the entries of the delegate queue indicates whether a corresponding one of the set of messaging queues is storing data.
    Type: Application
    Filed: April 23, 2015
    Publication date: October 27, 2016
    Inventors: Peter J. Wilson, Brian C. Kahne
  • Patent number: 9429070
    Abstract: System and method for starting a turbine engine are disclosed. These systems and methods for starting a turbine engine may be located on a vehicle, such as such as a Class 8 vehicle, equipped with a turbine engine as the prime mover or as a generator in a hybrid powertrain. In that regard, a fluid forcing device may be employed to start the turbine engine, such as an electric pump/compressor. The fluid forcing device may already be located on the vehicle for other purposes, and can include an electrically powered steering pump (also referred to as an electric pump) or an electrically powered air brake compressor (also referred to as an electric compressor). In order to start the turbine engine, the output of the electric pump/compressor drives an associated fluid circuit, which in turn, supplies fluid over a portion of the turbine shaft, wheel or scroll in order to impart rotational motion thereto. The rotational motion imparted to the turbine shaft, wheel or scroll aims to start the turbine engine.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: August 30, 2016
    Assignee: PACCAR Inc
    Inventors: William C. Kahn, Steve J. Polansky, Christopher G. Wehrwein
  • Patent number: 9430435
    Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A method for multi-protocol tunneling may include establishing a first communication path between ports of a switching fabric of a multi-protocol interconnect of a computer apparatus in response to a peripheral device being connected to the computer apparatus, establishing a second communication path between the switching fabric and a protocol-specific controller, and routing, by the multi-protocol interconnect, packets of a protocol of the peripheral device from the peripheral device to the protocol-specific controller over the first and second communication paths. Other embodiments may be described and claimed.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: August 30, 2016
    Assignee: INTEL CORPORATION
    Inventors: Prashant R. Chandra, Kevin C. Kahn, Eran Galil, Efraim Kugman, Naama Zolotov, Vladimir Yudovich, Yoni Dishon, Elli Bagelman
  • Patent number: 9292346
    Abstract: A processing system includes a processor pipeline, a detector circuit, and a task scheduler. The detector circuit includes a basic block detector circuit to determine that the processor pipeline received a first instruction of a first instance of a basic block, and to determine that a last-in-order instruction of the first instance of the basic block is a resource switch instruction (RSWI), and an indicator circuit to provide an indication in response to determining that the processor pipeline received the first instruction of a second instance of the basic block. The task scheduler initiates a resource switch, in response to the indication, at a time subsequent to the first instruction being received that is based on a cycle count that indicates a first number of processor cycles between receiving the first instruction and receiving the RSWI.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: James C. Holt, Brian C. Kahne, William C. Moyer