Abstract: A processing system includes a processor pipeline, a detector circuit, and a task scheduler. The detector circuit includes a basic block detector circuit to determine that the processor pipeline received a first instruction of a first instance of a basic block, and to determine that a last-in-order instruction of the first instance of the basic block is a resource switch instruction (RSWI), and an indicator circuit to provide an indication in response to determining that the processor pipeline received the first instruction of a second instance of the basic block. The task scheduler initiates a resource switch, in response to the indication, at a time subsequent to the first instruction being received that is based on a cycle count that indicates a first number of processor cycles between receiving the first instruction and receiving the RSWI.

Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A method for configuring a multi-protocol I/O interconnect may include identifying a plurality of switches of a switching fabric of a multi-protocol I/O interconnect, and configuring a path from a port of a first switch of the plurality of switches to a port of a second switch of the plurality of switches. Packets of a first protocol and packets of a second protocol, different from the first protocol, may be simultaneously routed over the path. Other embodiments may be described and claimed.

Abstract: Disclosed is a digital processor comprising an instruction memory having a first input, a second input, a first output, and a second output. A program counter register is in communication with the first input of the instruction memory. The program counter register is configured to store an address of an instruction to be fetched. A data pointer register is in communication with the second input of the instruction memory. The data pointer register is configured to store an address of a data value in the instruction memory. An instruction buffer is in communication with the first output of the instruction memory. The instruction buffer is arranged to receive an instruction according to a value at the program counter register. A data buffer is in communication with the second output of the instruction memory. The data buffer is arranged to receive a data value according to a value at the data pointer register.

Abstract: A system and method verifies and restores the consistency of inode to pathname mappings. In a first embodiment, an off-line verification procedure is modified to verify and correct the primary name inode to pathname mapping information within inodes of a file system. In a second embodiment, an on-line file system verification process is modified to verify inode to pathname mapping information upon the loading of each inode within the file system.

Abstract: An approach is provided in which an endianness violation detection sub-system detects endianness violations between hardware units. The endianness violation detection sub-system tracks memory operations performed by multiple hardware units via debug channels and generates lookup table entries that are stored in a lookup table. When the endianness violation detection sub-system detects endianness relevant load attributes of a load operation that are different than corresponding endianness relevant store attributes of a store operation, the endianness violation detection sub-system generates an endianness violation. In one embodiment, the endianness violation detection sub-system identifies an endianness violation when the endianness violation detection sub-system detects a difference in the byte ordering type between a hardware unit performing a store operation and a hardware unit performing a load operation.

Abstract: An on-disk storage arrangement increases the number of persistent consistency point images (PCPIs) that may be maintained for a volume of a storage system. The on-disk storage arrangement comprises a novel volume information (volinfo) block representing a root of the volume; the volinfo block is stored at predefined locations on disk and comprises various system wide configuration data. The volinfo block further comprises a data structure configured to provide a level of indirection that increases the number of PCPIs maintainable by a file system executing on the storage system. To that end, the data structure may be organized as an array of pointers, wherein each pointer references a block containing a snapshot root, thereby enabling efficient access to each PCPI maintained by the file system.

Abstract: Embodiments of a testcase checker system are disclosed herein. Embodiments of a testcase checker system may include an instruction set simulator configured to simulate execution of instructions of a testcase on a microprocessor using a reference model associated with an architecture of the microprocessor. The instruction set simulator may generate logging data associated with the each instruction based on the simulated execution of that instruction. The testcase checker system may also include checker module comprising a set of rules. Each of these rules may be associated with a boundedly undefined condition. The checker module is configured to receive the logging data associated with an instruction from the instruction set simulator and process the logging data based on the rules to determine if any of the rules are violated.

Abstract: An electrified engine accessory drive (EEAD) system is provided that replaces the front engine accessory drive (FEAD) components (e.g., a/c compressor, air brake compressor; power steering pump, etc.) on vehicles, such as heavy duty trucks. Using such an EEAD system aims to reduce parasitic losses induced on a conventional engine by the front engine accessory drive (FEAD) while providing additional benefits, such as engine off vehicle and/or system operation. The EEAD systems may also be used in lieu of rear-end accessory drives and other accessory drives powering multiple accessories from a common driveshaft.

Abstract: An approach is provided in which a set of common instructions are each executed by at least two processor cores. Each of the processor cores queues values resulting from at least one of the common instructions (a critical section). The queued values are compared by a queued comparator. An exception is issued in response to the comparison revealing unequal values having been queued by the processor cores.

Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A method for multi-protocol tunneling may include establishing a first communication path between ports of a switching fabric of a multi-protocol interconnect of a computer apparatus in response to a peripheral device being connected to the computer apparatus, establishing a second communication path between the switching fabric and a protocol-specific controller, and routing, by the multi-protocol interconnect, packets of a protocol of the peripheral device from the peripheral device to the protocol-specific controller over the first and second communication paths. Other embodiments may be described and claimed.

Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A switch includes a receive to receive a first message and a second message. The switch further includes first protocol logic to process the first message according to a first protocol and an adapter to process the second message according to a second protocol. The first protocol is different from the second protocol.

Abstract: A system and method maintains mappings from data containers to their parent directories within a file system of a storage system. Each inode is modified to include a primary name data structure comprising a parent directory inode and a parent directory cookie value. The parent directory cookie value identifies a particular directory entry within a specified block of a directory identified by parent directory inode. An alternate name file is utilized to store alternate names, such as those associated with hard links.

Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A method for managing flow across the multi-protocol I/O interconnect may include providing, by a first port of a switching fabric of a multi-protocol interconnect to a second port of the switching fabric, a first credit grant packet and a second credit grant packet as indications of unoccupied space of a buffer associated with a path between the first port and a second port, and simultaneously routing a first data packet of a first protocol and a second data packet of a second protocol, different from the first protocol, on the path from the second port to the first port based at least in part on receipt by the second port of the first and second credit grant packets. Other embodiments may be described and claimed.

Abstract: A processing system includes a processor configured to execute a plurality of instructions corresponding to a task, wherein the plurality of instructions comprises a resource transfer instruction to indicate a transfer of processing operations of the task from the processor to a different resource and a hint instruction which precedes the resource transfer instruction by a set of instructions within the plurality of instructions. A processor task scheduler is configured to schedule tasks to the processor, wherein, in response to execution of the hint instruction of the task, the processor task scheduler finalizes selection of a next task and loads a context of the selected next task into a background register file. The loading occurs concurrently with execution of the set of instructions between the hint instruction and resource transfer instruction, and, after loading is completed, the processor switches to the selected task in response to the resource transfer instruction.

Abstract: An electrified engine accessory drive (EEAD) system is provided that replaces the front engine accessory drive (FEAD) components (e.g., a/c compressor, air brake compressor; power steering pump, etc.) on vehicles, such as heavy duty trucks. Using such an EEAD system aims to reduce parasitic losses induced on a conventional engine by the front engine accessory drive (FEAD) while providing additional benefits, such as engine off vehicle and/or system operation. The EEAD systems may also be used in lieu of rear-end accessory drives and other accessory drives powering multiple accessories from a common driveshaft.

Abstract: System and method for starting a turbine engine are disclosed. These systems and methods for starting a turbine engine may be located on a vehicle, such as such as a Class 8 vehicle, equipped with a turbine engine as the prime mover or as a generator in a hybrid powertrain. In that regard, a fluid forcing device may be employed to start the turbine engine, such as an electric pump/compressor. The fluid forcing device may already be located on the vehicle for other purposes, and can include an electrically powered steering pump (also referred to as an electric pump) or an electrically powered air brake compressor (also referred to as an electric compressor). In order to start the turbine engine, the output of the electric pump/compressor drives an associated fluid circuit, which in turn, supplies fluid over a portion of the turbine shaft, wheel or scroll in order to impart rotational motion thereto. The rotational motion imparted to the turbine shaft, wheel or scroll aims to start the turbine engine.

Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A method for multi-protocol tunneling may include establishing a first communication path between ports of a switching fabric of a multi-protocol interconnect of a computer apparatus in response to a peripheral device being connected to the computer apparatus, establishing a second communication path between the switching fabric and a protocol-specific controller, and routing, by the multi-protocol interconnect, packets of a protocol of the peripheral device from the peripheral device to the protocol-specific controller over the first and second communication paths. Other embodiments may be described and claimed.

Abstract: An approach is provided in which a set of common instructions are each executed by at least two processor cores. Each of the processor cores queues values resulting from at least one of the common instructions (a critical section). The queued values are compared by a queued comparator. An exception is issued in response to the comparison revealing unequal values having been queued by the processor cores.

Abstract: Embodiments of a testcase checker system are disclosed herein. Embodiments of a testcase checker system may include an instruction set simulator configured to simulate execution of instructions of a testcase on a microprocessor using a reference model associated with an architecture of the microprocessor. The instruction set simulator may generate logging data associated with the each instruction based on the simulated execution of that instruction. The testcase checker system may also include checker module comprising a set of rules. Each of these rules may be associated with a boundedly undefined condition. The checker module is configured to receive the logging data associated with an instruction from the instruction set simulator and process the logging data based on the rules to determine if any of the rules are violated.

Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A multi-protocol I/O interconnect may include a switching fabric operatively coupled to a first protocol-specific controller and a second protocol-specific controller, and may be configured to simultaneously route packets of the first protocol to the first protocol-specific controller and packets of the second protocol to the second protocol-specific controller. Other embodiments may be described and claimed.