Abstract: A CMOS gate protection diode clamping the input terminal to substrate potential is prevented from injecting carriers into the substrate and causing SCR latchup by forming the diode as a well to substrate junction, surrounded by another, reverse-biased, well, to both reduce injection and collect parasitic injected carriers before they can diffuse to cause latchup.

Abstract: A data processing system includes a central processing subsystem, a main memory subsystem, and a number of peripheral subsystems including a communication subsystem all coupled in common to a system bus. Subsystems communicate with each other during asynchronously generated information bus transfer cycles. Each one of the subsystems receives information by providing any one of three signal responses including a positive acknowledge signal indicating an immediate response, a negative acknowledge signal indicating that the unit will most likely be busy for an extended period of time, and a quasi-negative response indicating that the unit will probably be ready during the next asynchronously generated bus transfer cycle.

Abstract: A sustained-release pharmaceutical tablet consisting essentially of drug pellets encapsulated with a water-soluble film-forming substance and a water-insoluble film-forming substance and blended and compressed into tablet form with a compressible tableting mixture and a process for preparation thereof are disclosed.

Abstract: A data processing system includes a number of input/output devices coupled to a communication multiplexer by 1 synchronous communication line and a number of asynchronous communication lines. During the polling operation, receive communication lines have high priority and transmit communication lines have low priority. Apparatus in the polling logic gives the synchronous communication line in the receive mode first priority and the synchronous communication line in the transmit mode second priority.

Abstract: A programmable communications processor is coupled to execute instructions of programs designed to process the transfer of information between a plurality of communication channels and a main memory included in the system. A software implemented and controlled pause counter enables the execution of a given maximum number of instructions for servicing, for example, a communication channel following which it suspends or pauses such servicing, in order to service another higher priority request which may be pending. Processing of lower priority service requests thus cannot delay the recognition and handling of higher priority requests for more than a minimum period of time and the effective throughput rate is increased.

Abstract: Firmware generated commands provided by a control store in a microprogrammed communications processor which is coupled in a system including a main memory and a central processing unit control the processing of instructions from the central processing unit, interrupts from the communications channels and servicing of such channels if a channel status change is detected. The firmware also controls the operation of the servicing of such channels by providing a control mechanism by which data is read from or written into the main memory. Further, interrupts which are not handled immediately are handled in a deferred interrupt arrangement.

Abstract: A paging apparatus includes addressing hardware for addressing a number of physical devices coupled to various communication buses, for mapping virtual addresses to real addresses, and controlling the flow of data. The paging apparatus generates 8 control signals, 5 of which modify a virtual address into a real address of a memory thereby expanding the capabilities of the real address from 256 address locations by an additional 512 address locations. The remaining 3 control signals control the flow of data by enabling or disabling data control apparatus in the physical devices.

Abstract: A remote maintenance apparatus for performing maintenance via a communication channel. Hardware is provided to retain information in a special channel which can be accessed by a remote communication system, in the event of malfunction in the computer system. An additional feature of this hardware is increased speed and efficiency in addressing when the computer system is operating normally.

Abstract: A multi-way vectored interrupt automatically addresses any one of a plurality of locations in a memory according to a unique function code. Hardware is provided which disables the normal paging addressing apparatus of a processor and enables an indirect addressing mechanism when a predetermined location in memory is addressed.

Abstract: In a method and apparatus for reconstructing Chinese characters such as in a printer system, each of the characters is divided into a pair of components at least one of which occurs in one or more other characters. The components which have a height equal to the height of a standard character cell are stored together with information as to the locations of the components across the width of the standard character cell for each character. The components may be stored in a compressed form, in which event the information as to their location forms a part of the compressed data. When a given character is to be reconstructed, the first component thereof is transferred to a buffer where it is temporarily stored at the proper location across the width of a standard character cell. Thereafter, the second component is transferred to a logic circuit together with the temporarily stored first component, and the two are logically OR'ed to form the complete character.

Abstract: A multistage amplifier having an automatically programmable gain is disclosed in which the amplifier gain is incremented in binary steps to a desired level. Each amplifier stage is switchable between a first and second gain in a binary sequence such that the four digit output of a sixteen bit counter will increment the total amplifier gain in sixteen binary steps.A readback and decoding circuit for reading magnetic tape is also disclosed in which the signal amplitude of data read from the magnetic tape is compared to a reference voltage which corresponds to the data readback clipping level. Only amplified data which exceeds the predetermined clipping level is gated out of the circuit for processing.