Patents by Inventor Carl J. Munkberg

Carl J. Munkberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9824412
    Abstract: In position-only shading, two geometry pipes exist, a trimmed down version called the Cull Pipe and a full version called the Replay Pipe. Thus, the Cull Pipe executes the position shaders in parallel with the main application, but typically generates the critical results much faster as it fetches and shades only the position attribute of the vertices and avoids the rasterization as well as the rendering of pixels for the frame buffer. Furthermore, the Cull Pipe uses these critical results to compute visibility information for all the triangles whether they are culled or not. On the other hand, the Replay Pipe consumes the visibility information to skip the culled triangles and shades only the visible triangles that are finally passed to the rasterization phase. Together the two pipes can hide the long cull runs of discarded triangles and can complete the work faster in some embodiments.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Saurabh Sharma, Subramaniam Maiyuran, Thomas A. Piazza, Kalyan K. Bhiravabhatla, Peter L. Doyle, Paul A. Johnson, Bimal Poddar, Jon N. Hasselgren, Carl J. Munkberg, Tomas G. Akenine-Moller, Harri Syrja, Kevin Rogovin, Robert L. Farrell
  • Publication number: 20170264106
    Abstract: According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 14, 2017
    Inventors: Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg
  • Patent number: 9761001
    Abstract: A layered, filtered shadow mapping algorithm may be used for motion blurred shadows. The algorithm is divided into two passes, namely a shadow pass and a lighting pass. The shadow pass renders the scene using stochastic rasterization and generates a time-dependent shadow map augmented with per-sample motion vectors. The subsequent lighting pass renders the scene from the camera's point of view, and performs a shadow query for each sample seen from the camera.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: September 12, 2017
    Assignee: Intel Corporation
    Inventors: Magnus Andersson, Jon N. Hasselgren, Carl J. Munkberg, Tomas Akenine-Moller
  • Publication number: 20170256079
    Abstract: According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering.
    Type: Application
    Filed: April 20, 2017
    Publication date: September 7, 2017
    Inventors: Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg
  • Patent number: 9754345
    Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of pixel region bit values are described.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventors: Tomas G Akenine-Moller, Jim K Nilsson, Prasoonkumar Surti, Jon N Hasselgren, Carl J Munkberg
  • Publication number: 20170206700
    Abstract: An apparatus and method are described for texture space shading. For example, one embodiment of a method comprises: performing texture mapping to map one or more textures to surfaces of one or more objects in texture space within a ray tracing architecture; and performing sampling and reconstruction directly on the surfaces of the objects in the texture space.
    Type: Application
    Filed: April 1, 2016
    Publication date: July 20, 2017
    Inventors: CARL J. MUNKBERG, JON N. HASSELGREN, FRANZ P. CLARBERG, MAGNUS ANDERSSON, ROBERT M. TOTH, JIM K. NILSSON, TOMAS G. AKENINE-MOLLER
  • Publication number: 20170178594
    Abstract: An apparatus and method for color buffer compression. For example, one embodiment of a method comprises: specifying a palette of available colors within a color space to be used for quantizing color values of pixels within a tile; subdividing the color space into a plurality of axis-aligned bucket regions, each of the available colors falling within one of the bucket regions; and quantizing the color values based on both the palette of available colors and the axis-aligned bucket regions.
    Type: Application
    Filed: December 19, 2015
    Publication date: June 22, 2017
    Inventors: JON N. HASSELGREN, CARL J. MUNKBERG
  • Publication number: 20170178398
    Abstract: An apparatus and method for extracting and using path shading coherence in a ray tracing architecture. For example, one embodiment of a graphics processing apparatus comprises: ray generation logic to generate a ray stream from one or more image tiles; ray sorting logic to sort the rays within the ray stream based on a material identifier (ID) associated with each of the rays to generate a sorted ray stream; and one or more shaders to perform shading operations on rays within the sorted ray stream in an order in which the rays are sorted within the sorted ray stream.
    Type: Application
    Filed: December 19, 2015
    Publication date: June 22, 2017
    Inventors: ATTILA T. AFRA, CARL J. MUNKBERG
  • Patent number: 9672657
    Abstract: Real-time light field reconstruction for defocus blur may be used to handle the case of simultaneous defocus and motion blur. By carefully introducing a few approximations, a very efficient sheared reconstruction filter is derived, which produces high quality images even for a very low number of input samples in some embodiments. The algorithm may be temporally robust, and is about two orders of magnitude faster than previous work, making it suitable for both real-time rendering and as a post-processing pass for high quality rendering in some embodiments.
    Type: Grant
    Filed: September 10, 2016
    Date of Patent: June 6, 2017
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Karthik Vaidyanathan, Jon N. Hasselgren, Franz P. Clarberg, Tomas G. Akenine-Moller, Marco Salvi
  • Patent number: 9659393
    Abstract: According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg
  • Publication number: 20170124742
    Abstract: Cache thrashing or over-accessing of a cache can be reduced by reversing the order of traversal of a triangle on different granularities. In the case where triangles are not grouped, the traverse order may be reversed on each triangle. In cases where triangles are grouped, the traversal order may be reversed with each group change. However, when motion is excessive, for example beyond a threshold, then the traversal order reversal may be disabled.
    Type: Application
    Filed: October 29, 2015
    Publication date: May 4, 2017
    Inventors: Jon N. Hasselgren, Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg, Jim K. Nilsson
  • Patent number: 9569879
    Abstract: We present a new culling test for rasterization of simultaneous depth of field and motion blur, which efficiently reduces the set of (x, y, u, v, t) samples that need to be coverage tested within a screen space tile. The test finds linear bounds in u, t space and v, t space respectively, using a separating line algorithm. This test is part of the foundation for an efficient 5D rasterizer that extracts coherence in both defocus and motion blur to minimize the number of visibility tests.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: February 14, 2017
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Tomas G. Akenine-Moller, Jon N. Hasselgren
  • Patent number: 9569878
    Abstract: Thin invention introduces a five-dimensional rasterization technique that uses a test based on triangle edges in order to obtain high efficiency. A compact formulation of five-dimensional edge equations is used to derive a conservative triangle edge versus tile test in five dimensions, expressed as an affine hyperplane.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: February 14, 2017
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Franz P. Clarberg
  • Publication number: 20170011545
    Abstract: Real-time light field reconstruction for defocus blur may be used to handle the case of simultaneous defocus and motion blur. By carefully introducing a few approximations, a very efficient sheared reconstruction filter is derived, which produces high quality images even for a very low number of input samples in some embodiments. The algorithm may be temporally robust, and is about two orders of magnitude faster than previous work, making it suitable for both real-time rendering and as a post-processing pass for high quality rendering in some embodiments.
    Type: Application
    Filed: September 10, 2016
    Publication date: January 12, 2017
    Inventors: Carl J. Munkberg, Karthik Vaidyanathan, Jon N. Hasselgren, Franz P. Clarberg, Tomas G. Akenine-Moller, Marco Salvi
  • Patent number: 9501864
    Abstract: Because using the same number of bits per residual depth offset compression is not the best distribution of bits, the bits per residual may be distributed instead according to the content of the depths of a tile. For example, if the depth differences close to the Zmax are small, then fewer bits can be spent on residuals for the samples that are encoded relative to Zmax. Consequently, more bits can be spent on the residuals for the samples that are encoded relative to Zmin. As a result, more tiles succeed at compressing to the required number of bits.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Magnus Andersson, Jon N. Hasselgren, Carl J. Munkberg, Robert M. Toth
  • Patent number: 9483869
    Abstract: Real-time light field reconstruction for defocus blur may be used to handle the case of simultaneous defocus and motion blur. By carefully introducing a few approximations, a very efficient sheared reconstruction filter is derived, which produces high quality images even for a very low number of input samples in some embodiments. The algorithm may be temporally robust, and is about two orders of magnitude faster than previous work, making it suitable for both real-time rendering and as a post-processing pass for high quality rendering in some embodiments.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: November 1, 2016
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Karthik Vaidyanathan, Jon N. Hasselgren, Franz P. Clarberg, Tomas G. Akenine-Moller, Marco Salvi
  • Patent number: 9465212
    Abstract: User-controllable defocus blur for a stochastic rasterizer may be implemented by modifying circle of confusion coefficients per vertex to express more general defocus blur. The method can be applied to limit the foreground blur, extend the in-focus range, simulate tilt-shift photography, and specify per-object defocus blur. Furthermore, with two simplifying assumptions, existing triangle coverage tests and tile culling tests can be used with very modest modifications.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: October 11, 2016
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Robert M. Toth
  • Patent number: 9466090
    Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of indexed subsets are described. In one example, compression in graphics rendering may include determining a plurality of color values associated with individual pixels of a tile of pixels, generating a subset of the plurality of color values such that the subset of the plurality of color values include one or more distinct color values from the plurality of color values, associating an index value with each color value of the subset of the plurality of color values, determining, for each of the individual pixels, an associated pixel index value to generate a plurality of pixel index values associated with the individual pixels of the tile of pixels, storing, in memory, graphics data including the subset of the plurality of color values, the associated index values, and the plurality of pixel index values.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: October 11, 2016
    Assignee: INTEL CORPORATION
    Inventors: Prasoonkumar Surti, Tomas G. Akenine-Moller, Jon N. Hasselgren, Carl J. Munkberg, Jim. K. Nilsson
  • Patent number: 9406100
    Abstract: Techniques are described that can delay or even prevent use of memory to store triangles associated with tiles as well as processing resources associated with vertex shading and binning triangles. The techniques can also provide better load balancing among a set of cores, and hence provide better performance. A bounding volume is generated to represent a geometry group. Culling takes place to determine whether a geometry group is to have triangles rendered. Vertex shading and association of triangles with tiles can be performed across multiple cores in parallel. Processing resources are allocated for rasterizing tiles whose triangles have been vertex shaded and binned over tiles whose triangles have yet to be vertex shaded and binned. Rasterization of triangles of different tiles can be performed by multiple cores in parallel.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: August 2, 2016
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Jon N. Hasselgren, Carl J. Munkberg, Franz P. Clarberg
  • Patent number: 9401046
    Abstract: Micropolygon splatting may involve tessellating by subdividing a mesh until triangle edges are shorter than 0.75 pixels. In some cases, rasterizing the primitive may be avoided.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: July 26, 2016
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Tomas G. Akenine-Möller, Jon N. Hasselgren, Robert M. Toth