Patents by Inventor Carl J. Munkberg

Carl J. Munkberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9396582
    Abstract: A per-tile test in the 5D rasterizer outputs intervals for both lens parameters, (u,v), and for time, t, as well as for depth z. These intervals are conservative bounds for the current tile for 1) the visible lens region, 2) the time the triangle overlaps the tile, and 3) the depth range for the triangle inside the tile.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: July 19, 2016
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Jim K. Nilsson, Carl J. Munkberg
  • Patent number: 9390550
    Abstract: Efficient overlap tests between a screen space tile and a moving triangle with per-vertex motion following Bézier curves report conservative time bounds in which the moving triangle overlaps with a tile. The tests can be used in designing efficient hierarchical traversal algorithms for higher order motion blur rendering.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Jon N. Hasselgren, Tomas G. Akenine-Moller
  • Patent number: 9390541
    Abstract: In accordance with some embodiments, a tile shader executes on a group of pixels prior to a pixel shader. The tile of pixels may be rectangular in some embodiments. The tile may be executed hierarchically, refining each tile into smaller subtiles until the pixel or sample level is reached. The tile shader program can be written to discard groups of pixels, thereby quickly removing areas of the bounding triangles that lie outside the shape being rasterized or quickly discarding groups of pixel shader executions that will not contribute to the final image.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Jon N. Hasselgren, Tomas G. Akenine-Moller, Carl J. Munkberg, Jim K. Nilsson, Robert M. Toth, Franz P. Clarberg
  • Publication number: 20160189338
    Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of pixel region bit values are described.
    Type: Application
    Filed: March 3, 2016
    Publication date: June 30, 2016
    Inventors: Tomas G. AKENINE-MOLLER, Jim K. NILSSON, Prasoonkumar SURTI, Jon N. HASSELGREN, Carl J. MUNKBERG
  • Publication number: 20160133045
    Abstract: In accordance with some embodiments, a zero coverage test may determine whether a primitive such as a triangle relies on lanes between rows or columns or lines of samples. If so, the primitive can be culled in a zero coverage culling test.
    Type: Application
    Filed: November 6, 2014
    Publication date: May 12, 2016
    Inventors: Tomas G. Akenine-Moller, Jon N. Hasselgren, Carl J. Munkberg
  • Patent number: 9317964
    Abstract: Depth of field may be rasterized by culling half-space regions on a lens from which a triangle to be rendered is not visible. Then, inside tests are only performed on the remaining unculled half-space regions. Separating planes between the triangle to be rendered and the tile being processed can be used to define the half-space regions.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: April 19, 2016
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Carl J. Munkberg, Jon N. Hasselgren, Robert M. Toth
  • Patent number: 9305368
    Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of pixel region bit values are described.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: April 5, 2016
    Assignee: INTEL CORPORATION
    Inventors: Tomas G. Akenine-Moller, Jim K. Nilsson, Prasoonkumar Surti, Jon N. Hasselgren, Carl J. Munkberg
  • Publication number: 20160093098
    Abstract: A layered, filtered shadow mapping algorithm may be used for motion blurred shadows. The algorithm is divided into two passes, namely a shadow pass and a lighting pass. The shadow pass renders the scene using stochastic rasterization and generates a time-dependent shadow map augmented with per-sample motion vectors. The subsequent lighting pass renders the scene from the camera's point of view, and performs a shadow query for each sample seen from the camera.
    Type: Application
    Filed: December 18, 2014
    Publication date: March 31, 2016
    Inventors: Magnus Andersson, Jon N. Hasselgren, Carl J. Munkberg, Tomas Akenine-Moller
  • Publication number: 20160086299
    Abstract: In position-only shading, two geometry pipes exist, a trimmed down version called the Cull Pipe and a full version called the Replay Pipe. Thus, the Cull Pipe executes the position shaders in parallel with the main application, but typically generates the critical results much faster as it fetches and shades only the position attribute of the vertices and avoids the rasterization as well as the rendering of pixels for the frame buffer. Furthermore, the Cull Pipe uses these critical results to compute visibility information for all the triangles whether they are culled or not. On the other hand, the Replay Pipe consumes the visibility information to skip the culled triangles and shades only the visible triangles that are finally passed to the rasterization phase. Together the two pipes can hide the long cull runs of discarded triangles and can complete the work faster in some embodiments.
    Type: Application
    Filed: September 24, 2014
    Publication date: March 24, 2016
    Inventors: Saurabh Sharma, Subramaniam Maiyuran, Thomas A. Piazza, Kalyan K. Bhiravabhatla, Peter L. Doyle, Paul A. Johnson, Bimal Poddar, Jon N. Hasselgren, Carl J. Munkberg, Tomas G. Akenine-Moller, Harri Syrja, Kevin Rogovin, Robert L. Farrell
  • Publication number: 20160055614
    Abstract: Techniques are described that can delay or even prevent use of memory to store triangles associated with tiles as well as processing resources associated with vertex shading and binning triangles. The techniques can also provide better load balancing among a set of cores, and hence provide better performance. A bounding volume is generated to represent a geometry group. Culling takes place to determine whether a geometry group is to have triangles rendered. Vertex shading and association of triangles with tiles can be performed across multiple cores in parallel. Processing resources are allocated for rasterizing tiles whose triangles have been vertex shaded and binned over tiles whose triangles have yet to be vertex shaded and binned. Rasterization of triangles of different tiles can be performed by multiple cores in parallel.
    Type: Application
    Filed: November 3, 2015
    Publication date: February 25, 2016
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Jon N. Hasselgren, Carl J. Munkberg, Franz P. Clarberg
  • Publication number: 20160054790
    Abstract: In accordance with some embodiments, the knowledge that a capped frame time is used can be exploited to reduce power consumption. Generally a capped frame time is a pre-allocated amount of time to apply power for rendering in graphics processing. Generally the frame time involves the application of power and some down time in which only idle power is applied pending the next frame time. By making better use of that down time, power consumption reductions can be achieved in some embodiments.
    Type: Application
    Filed: November 2, 2015
    Publication date: February 25, 2016
    Inventors: Tomas G. Akenine-Moller, Bjorn Johnsson, Magnus Andersson, Jim K. Nilsson, Robert M. Toth, Carl J. Munkberg, Jon N. Hasselgren
  • Patent number: 9251731
    Abstract: Techniques related to graphics rendering including techniques for improved multi-sampling anti-aliasing compression by use of unreachable bit combinations as described.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: February 2, 2016
    Assignee: INTEL CORPORATION
    Inventors: Tomas G. Akenine-Moller, Prasoonkumar Surti, Carl J. Munkberg
  • Patent number: 9201487
    Abstract: In accordance with some embodiments, the knowledge that a capped frame time is used can be exploited to reduce power consumption. Generally a capped frame time is a pre-allocated amount of time to apply power for rendering in graphics processing. Generally the frame time involves the application of power and some down time in which only idle power is applied pending the next frame time. By making better use of that down time, power consumption reductions can be achieved in some embodiments.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: December 1, 2015
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Bjorn Johnsson, Magnus Andersson, Jim K. Nilsson, Robert M. Toth, Carl J. Munkberg, Jon N. Hasselgren
  • Publication number: 20150326862
    Abstract: First, the colors are partitioned within a tile into distinct groups, such that the variation of color within each group is lowered. Second, each group can be encoded in an efficient manner. The algorithm described herein may give a higher compression ratio than previous algorithms, and therefore may further reduce memory bandwidth at a very low increase in computational cost in some embodiments. The algorithm may be added to a system with existing buffer compression algorithms, handling additional tiles that the existing algorithm fails to compress, thereby increasing the overall compression rate.
    Type: Application
    Filed: May 6, 2014
    Publication date: November 12, 2015
    Inventors: Tomas G. Akenine-Moller, Jon N. Hasselgren, Carl J. Munkberg
  • Patent number: 9183652
    Abstract: Cache thrashing or over-accessing of a cache can be reduced by reversing the order of traversal of a triangle on different granularities. In the case where triangles are not grouped, the traverse order may be reversed on each triangle. In cases where triangles are grouped, the traversal order may be reversed with each group change. However, when motion is excessive, for example beyond a threshold, then the traversal order reversal may be disabled.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: November 10, 2015
    Assignee: Intel Corporation
    Inventors: Jon N. Hasselgren, Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg, Jim K. Nilsson
  • Patent number: 9183608
    Abstract: Techniques are described that can delay or even prevent use of memory to store triangles associated with tiles as well as processing resources associated with vertex shading and binning triangles. The techniques can also provide better load balancing among a set of cores, and hence provide better performance. A bounding volume is generated to represent a geometry group. Culling takes place to determine whether a geometry group is to have triangles rendered. Vertex shading and association of triangles with tiles can be performed across multiple cores in parallel. Processing resources are allocated for rasterizing tiles that have been vertex shaded and binned triangles over tiles that have yet to be vertex shaded and binned triangles. Rasterization of triangles of different tiles can be performed by multiple cores in parallel.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: November 10, 2015
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Jon N. Hasselgren, Carl J. Munkberg, Franz P. Clarberg
  • Patent number: 9165348
    Abstract: Depth of field may be rasterized by culling half-space regions on a lens from which a triangle to be rendered is not visible. Then, inside tests are only performed on the remaining unculled half-space regions. Separating planes between the triangle to be rendered and the tile being processed can be used to define the half-space regions.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: October 20, 2015
    Assignee: Intel Corporation
    Inventors: Robert M. Toth, Tomas G. Akenine-Moller, Carl J. Munkberg
  • Publication number: 20150287238
    Abstract: Depth of field may be rasterized by culling half-space regions on a lens from which a triangle to be rendered is not visible. Then, inside tests are only performed on the remaining unculled half-space regions. Separating planes between the triangle to be rendered and the tile being processed can be used to define the half-space regions.
    Type: Application
    Filed: April 16, 2015
    Publication date: October 8, 2015
    Inventors: Tomas G. Akenine-Moller, Carl J. Munkberg, Jon N. Hasselgren, Robert M. Toth
  • Publication number: 20150279092
    Abstract: A system rapidly builds bounding volume hierarchies for ray tracing using both the CPU cores and an integrated graphics processor. The hierarchy is built directly into shared memory (between the CPU and GPU). The method starts by sorting the triangles along a space-filling curve, and then quickly sets up a number of mini-trees with a small number of triangles in them, which includes computing the bounding boxes of the mini-trees. This makes it possible to build the mini-trees using a surface-area heuristic in parallel on the graphics processor, while at the same time, the trees above the mini-trees are built in a top-down fashion using the CPU cores.
    Type: Application
    Filed: December 18, 2014
    Publication date: October 1, 2015
    Inventors: Per Ganestam, Tomas Akenine-Moller, Carl J. Munkberg
  • Patent number: 9142008
    Abstract: Motion blur rasterization may involve executing a first test for each plane of a tile frustum. The first test is a frustum plane versus moving bounding box overlap test where planes bounding a moving primitive are overlap tested against a screen tile frustum. According to a second test executed after the first test, for primitive edges against tile corners, the second test is a tile corner versus moving edge overlap test. The corners of the screen space tile are tested against a moving triangle edge in two-dimensional homogeneous space.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: September 22, 2015
    Assignee: Intel Corporation
    Inventors: Franz P. Clarberg, Carl J. Munkberg, Jon N. Hasselgren, Tomas G. Akenine-Moller