Patents by Inventor Carl J. Munkberg

Carl J. Munkberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9111392
    Abstract: Unlike a static primitive, where the depth function is planar, the depth function for a moving and defocused triangle is a rational function in time and the lens parameters. Compact depth functions can be used to design an efficient depth buffer compressor/decompressor, which significantly lowers total depth buffer bandwidth usage. In addition, this compressor/decompressor is substantially simpler in the number of operations needed to execute, which makes it more amenable for hardware implementation than previous methods.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 18, 2015
    Assignee: Intel Corporation
    Inventors: Magnus Andersson, Carl J. Munkberg, Tomas G. Akenine-Moller, Jon N. Hasselgren
  • Publication number: 20150206340
    Abstract: Real-time light field reconstruction for defocus blur may be used to handle the case of simultaneous defocus and motion blur. By carefully introducing a few approximations, a very efficient sheared reconstruction filter is derived, which produces high quality images even for a very low number of input samples in some embodiments. The algorithm may be temporally robust, and is about two orders of magnitude faster than previous work, making it suitable for both real-time rendering and as a post-processing pass for high quality rendering in some embodiments.
    Type: Application
    Filed: May 12, 2014
    Publication date: July 23, 2015
    Inventors: Carl J. Munkberg, Karthik Vaidyanathan, Jon N. Hasselgren, Franz P. Clarberg, Tomas G. Akenine-Moller, Marco Salvi
  • Publication number: 20150187124
    Abstract: Because using the same number of bits per residual depth offset compression is not the best distribution of bits, the bits per residual may be distributed instead according to the content of the depths of a tile. For example, if the depth differences close to the Zmax are small, then fewer bits can be spent on residuals for the samples that are encoded relative to Zmax. Consequently, more bits can be spent on the residuals for the samples that are encoded relative to Zmin. As a result, more tiles succeed at compressing to the required number of bits.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Inventors: Tomas G. Akenine-Moller, Magnus Andersson, Jon N. Hasselgren, Carl J. Munkberg, Robert M. Toth
  • Patent number: 9058697
    Abstract: Depth of field may be rasterized by culling half-space regions on a lens from which a triangle to be rendered is not visible. Then, inside tests are only performed on the remaining unculled half-space regions. Separating planes between the triangle to be rendered and the tile being processed can be used to define the half-space regions.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: June 16, 2015
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Möller, Carl J. Munkberg, Jon N. Hasselgren, Robert M. Toth
  • Publication number: 20150154772
    Abstract: Cache thrashing or over-accessing of a cache can be reduced by reversing the order of traversal of a triangle on different granularities. In the case where triangles are not grouped, the traverse order may be reversed on each triangle. In cases where triangles are grouped, the traversal order may be reversed with each group change. However, when motion is excessive, for example beyond a threshold, then the traversal order reversal may be disabled.
    Type: Application
    Filed: May 13, 2013
    Publication date: June 4, 2015
    Inventors: Jon N. Hasselgren, Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg, Jim K. Nilsson
  • Publication number: 20150145873
    Abstract: Techniques are described that can delay or even prevent use of memory to store triangles associated with tiles as well as processing resources associated with vertex shading and binning triangles. The techniques can also provide better load balancing among a set of cores, and hence provide better performance. A bounding volume is generated to represent a geometry group. Culling takes place to determine whether a geometry group is to have triangles rendered. Vertex shading and association of triangles with tiles can be performed across multiple cores in parallel. Processing resources are allocated for rasterizing tiles that have been vertex shaded and binned triangles over tiles that have yet to be vertex shaded and binned triangles. Rasterization of triangles of different tiles can be performed by multiple cores in parallel.
    Type: Application
    Filed: December 23, 2009
    Publication date: May 28, 2015
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Jon N. Hasselgren, Carl J. Munkberg, Franz P. Clarberg
  • Patent number: 9038034
    Abstract: During compilation, the interval bounds for a programmable culling unit are calculated if possible. For each variable, interval bounds are calculated during the compilation, and the bounds together with other metadata are used to generate an optimized culling program. If not possible, then an assumption may be made and the assumption used to compile the code. If the assumption proves to be invalid, a new assumption could be made and the code may be recompiled in some embodiments.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: May 19, 2015
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Jon N. Hasselgren, Carl J. Munkberg, Franz P. Clarberg, Robert M. Toth
  • Publication number: 20150097857
    Abstract: According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering.
    Type: Application
    Filed: October 7, 2013
    Publication date: April 9, 2015
    Inventors: Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg
  • Publication number: 20150070355
    Abstract: An architecture for pixel shading, enables flexible control of shading rates and automatic shading reuse between triangles in tessellated primitives in some embodiments. The cost of pixel shading may then be decoupled from the geometric complexity. Wider use of tessellation and fine geometry may be made more feasible, even at very limited power budgets. Shading may be done over small local grids in parametric patch space, with reusing of shading for nearby samples. The decomposition of shaders into multiple parts is supported, which parts are shaded at different frequencies. Shading rates can be locally and adaptively controlled, in order to direct the computations to visually important areas and to provide performance scaling with a graceful degradation of quality. Another important benefit, in some embodiments, of shading in patch space is that it allows efficient rendering of distribution effects, which further closes the gap between real-time and offline rendering.
    Type: Application
    Filed: March 27, 2014
    Publication date: March 12, 2015
    Inventors: Franz P. Clarberg, Tomas G. Akenine-Moller, Robert M. Toth, Carl J. Munkberg
  • Publication number: 20150022532
    Abstract: Motion blur rasterization may involve executing a first test for each plane of a tile frustum. The first test is a frustum plane versus moving bounding box overlap test where planes bounding a moving primitive are overlap tested against a screen tile frustum. According to a second test executed after the first test, for primitive edges against tile corners, the second test is a tile corner versus moving edge overlap test. The corners of the screen space tile are tested against a moving triangle edge in two-dimensional homogeneous space.
    Type: Application
    Filed: September 10, 2014
    Publication date: January 22, 2015
    Inventors: Franz P. Clarberg, Carl J. Munkberg, Jon N. Hasselgren, Tomas G. Akenine-Moller
  • Publication number: 20140375665
    Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of indexed subsets are described.
    Type: Application
    Filed: June 20, 2013
    Publication date: December 25, 2014
    Inventors: Prasoonkumar Surti, Tomas G. Akenine-Moller, Jon N. Hasselgren, Carl J. Munkberg, Jim K. Nilsson
  • Publication number: 20140375666
    Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of pixel region bit values are described.
    Type: Application
    Filed: June 21, 2013
    Publication date: December 25, 2014
    Inventors: Tomas G. Akenine-Moller, Jim K. Nilsson, Prasoonkumar Surti, Jon N. Hasselgren, Carl J. Munkberg
  • Publication number: 20140333662
    Abstract: Techniques related to graphics rendering including techniques for improved multi-sampling anti-aliasing compression by use of unreachable bit combinations ae described.
    Type: Application
    Filed: May 10, 2013
    Publication date: November 13, 2014
    Inventors: Tomas G. Akenine-Moller, Prasoonkumar Surti, Carl J. Munkberg
  • Publication number: 20140313194
    Abstract: Efficient overlap tests between a screen space tile and a moving triangle with per-vertex motion following Bézier curves report conservative time bounds in which the moving triangle overlaps with a tile. The tests can be used in designing efficient hierarchical traversal algorithms for higher order motion blur rendering.
    Type: Application
    Filed: October 17, 2013
    Publication date: October 23, 2014
    Inventors: Carl J. Munkberg, Jon N. Hasselgren, Tomas G. Akenine-Moller
  • Publication number: 20140300619
    Abstract: In accordance with some embodiments, a tile shader executes on a group of pixels prior to a pixel shader. The tile of pixels may be rectangular in some embodiments. The tile may be executed hierarchically, refining each tile into smaller subtiles until the pixel or sample level is reached. The tile shader program can be written to discard groups of pixels, thereby quickly removing areas of the bounding triangles that lie outside the shape being rasterized or quickly discarding groups of pixel shader executions that will not contribute to the final image.
    Type: Application
    Filed: April 9, 2013
    Publication date: October 9, 2014
    Inventors: Jon N. Hasselgren, Tomas G. Akenine-Moller, Carl J. Munkberg, Jim K. Nilsson, Robert M. Toth, Franz P. Clarberg
  • Patent number: 8854377
    Abstract: Motion blur rasterization may involve executing a first test for each plane of a tile frustum. The first test is a frustum plane versus moving bounding box overlap test where planes bounding a moving primitive are overlap tested against a screen tile frustum. According to a second test executed after the first test, for primitive edges against tile corners, the second test is a tile corner versus moving edge overlap test. The corners of the screen space tile are tested against a moving triangle edge in two-dimensional homogeneous space.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: October 7, 2014
    Assignee: Intel Corporation
    Inventors: Franz P. Clarberg, Carl J. Munkberg, Jon N. Hasselgren, Tomas G. Akenine-Möller
  • Patent number: 8842121
    Abstract: A single instruction multiple data (SIMD) processor with a given width may operate on registers of the same width completely filled with fragments. A parallel set of registers are loaded and tested. The fragments that fail are eliminated and the register set is refilled from the parallel set.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: September 23, 2014
    Assignee: Intel Corporation
    Inventors: Tomas Akenine-Möller, Jon N. Hasselgren, Carl J. Munkberg, Robert M. Toth, Franz P. Clarberg
  • Publication number: 20140258754
    Abstract: In accordance with some embodiments, the knowledge that a capped frame time is used can be exploited to reduce power consumption. Generally a capped frame time is a pre-allocated amount of time to apply power for rendering in graphics processing. Generally the frame time involves the application of power and some down time in which only idle power is applied pending the next frame time. By making better use of that down time, power consumption reductions can be achieved in some embodiments.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 11, 2014
    Inventors: Tomas G. Akenine-Moller, Bjorn Johnsson, Magnus Andersson, Jim K. Nilsson, Robert M. Toth, Carl J. Munkberg, Jon N. Hasselgren
  • Publication number: 20140132596
    Abstract: We present a new culling test for rasterization of simultaneous depth of field and motion blur, which efficiently reduces the set of (x, y, u, v, t) samples that need to be coverage tested within a screen space tile. The test finds linear bounds in u, t space and v, t space respectively, using a separating line algorithm. This test is part of the foundation for an efficient 5D rasterizer that extracts coherence in both defocus and motion blur to minimize the number of visibility tests.
    Type: Application
    Filed: May 31, 2012
    Publication date: May 15, 2014
    Inventors: Carl J. Munkberg, Tomas G. Akenine-Moller, Jon N. Hasselgren
  • Publication number: 20140085300
    Abstract: Unlike a static primitive, where the depth function is planar, the depth function for a moving and defocused triangle is a rational function in time and the lens parameters. Compact depth functions can be used to design an efficient depth buffer compressor/decompressor, which significantly lowers total depth buffer bandwidth usage. In addition, this compressor/decompressor is substantially simpler in the number of operations needed to execute, which makes it more amenable for hardware implementation than previous methods.
    Type: Application
    Filed: December 20, 2012
    Publication date: March 27, 2014
    Inventors: Magnus Andersson, Carl J. Munkberg, Tomas G. Akenine-Moller, Jon N. Hasselgren