Patents by Inventor Carsten Ahrens

Carsten Ahrens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7253492
    Abstract: A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged on top of the second insulator layer, a backside metal layer deposited on the bottom surface of the substrate, a first via structure extending from the bottom surface of the substrate to the top of the first insulating layer between the backside layer and the runner, and a second via extending from the top of the first insulating layer to the top of the second insulating layer between the first via and the runner.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: August 7, 2007
    Assignee: Infineon Technologies AG
    Inventors: Gordon Ma, Carsten Ahrens
  • Patent number: 7221034
    Abstract: A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged on top of the second insulator layer, a backside metal layer deposited on the bottom surface of the substrate, a first via structure extending from the bottom surface of the substrate to the top of the first insulating layer between the backside layer and the runner, and a second via extending from the top of the first insulating layer to the top of the second insulating layer between the first via and the runner.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: May 22, 2007
    Assignee: Infineon Technologies AG
    Inventors: Gordon Ma, Carsten Ahrens
  • Patent number: 7176546
    Abstract: A diode circuit includes a pin diode structure, wherein the n-semiconductor layer is a buried layer, on which the i-area is deposited by an epitaxy method, and wherein a p-semiconductor layer is introduced into the epitaxy layer. A contacting of the p-semiconductor layer and a contacting of the n-semiconductor layer are arranged on the same main surface of the semiconductor substrate so that an integration with an integrated capacitor, an integrated resistor and/or an integrated inductor is possible.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: February 13, 2007
    Assignee: Infineon Technologies AG
    Inventors: Carsten Ahrens, Wolfgang Hartung, Holger Heuermann, Reinhard Losehand, Josef-Paul Schaffer
  • Patent number: 7176128
    Abstract: A method for producing a contact structure on a structured surface comprising producing a first conductive layer on the structured surface, wherein the first conductive layer comprising tungsten. A conductive seed layer is produced on the first conductive layer, the contact structure being produced by electroplating on the seed layer. The first conductive layer serves as an etch stop for selectively removing substrate material from the backside.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: February 13, 2007
    Assignee: Infineon Technologies AG
    Inventors: Carsten Ahrens, Jakob Huber, Uwe Seidel
  • Publication number: 20070020863
    Abstract: A semiconductor device comprises a semiconductor substrate, an insulating layer on top of the substrate, a lateral field effect transistor comprising a drain region and a source region arranged in the substrate and a gate arranged above the substrate within the insulating layer, a drain runner arranged on top of the insulator layer above the drain region, a source runner arranged on top of the insulator layer above the source region, a gate runner arranged on top of the insulator layer outside an area defined by the drain runner and the source runner, a first coupling structure comprising a via for coupling the drain runner with the drain region, and a second coupling structure comprising a via for coupling the source runner with the source region.
    Type: Application
    Filed: September 14, 2006
    Publication date: January 25, 2007
    Inventors: Gordon Ma, Carsten Ahrens
  • Publication number: 20070007616
    Abstract: A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged on top of the second insulator layer, a backside metal layer deposited on the bottom surface of the substrate, a first via structure extending from the bottom surface of the substrate to the top of the first insulating layer between the backside layer and the runner, and a second via extending from the top of the first insulating layer to the top of the second insulating layer between the first via and the runner.
    Type: Application
    Filed: September 13, 2006
    Publication date: January 11, 2007
    Inventors: Gordon Ma, Carsten Ahrens
  • Patent number: 7119399
    Abstract: A semiconductor device has a semiconductor substrate, an insulating layer on top of the substrate, a lateral field effect transistor with a drain region and a source region arranged in the substrate and a gate arranged above the substrate within the insulating layer, a drain runner arranged on top of the insulator layer above the drain region, a source runner arranged on top of the insulator layer above the source region, a gate runner arranged on top of the insulator layer outside an area defined by the drain runner and the source runner, a first coupling structure with a via for coupling the drain runner with the drain region, and a second coupling structure with a via for coupling the source runner with the source region.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: October 10, 2006
    Assignee: Infineon Technologies AG
    Inventors: Gordon Ma, Carsten Ahrens
  • Patent number: 7030457
    Abstract: A capacitor includes a semiconductor substrate in which a trench is formed through which the substrate is doped. A dielectric layer covers the surface of the trench, wherein furthermore an electrically conductive material is arranged in the trench. A first contact structure for contacting the electrically conductive material in the trench in an electrically conductive manner and a second contact structure for contacting the doped semiconductor substrate in an electrically conductive manner are also formed in the capacitor. The capacitor has low series resistance of the electrodes and may be produced in a simple manner.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: April 18, 2006
    Assignee: Infineon Technologies AG
    Inventors: Carsten Ahrens, Angelika Geiselbrechtinger, Wolfgang Hartung, Christian Herzum, Reinhard Losehand
  • Publication number: 20050189588
    Abstract: A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged on top of the second insulator layer, a backside metal layer deposited on the bottom surface of the substrate, a first via structure extending from the bottom surface of the substrate to the top of the first insulating layer between the backside layer and the runner, and a second via extending from the top of the first insulating layer to the top of the second insulating layer between the first via and the runner.
    Type: Application
    Filed: February 27, 2004
    Publication date: September 1, 2005
    Inventors: Gordon Ma, Carsten Ahrens
  • Publication number: 20050189587
    Abstract: A semiconductor device comprises a semiconductor substrate, an insulating layer on top of the substrate, a lateral field effect transistor comprising a drain region and a source region arranged in the substrate and a gate arranged above the substrate within the insulating layer, a drain runner arranged on top of the insulator layer above the drain region, a source runner arranged on top of the insulator layer above the source region, a gate runner arranged on top of the insulator layer outside an area defined by the drain runner and the source runner, a first coupling structure comprising a via for coupling the drain runner with the drain region, and a second coupling structure comprising a via for coupling the source runner with the source region.
    Type: Application
    Filed: February 27, 2004
    Publication date: September 1, 2005
    Inventors: Gordon Ma, Carsten Ahrens
  • Publication number: 20050153546
    Abstract: A method for producing a contact structure on a structured surface comprising producing a first conductive layer on the structured surface, wherein the first conductive layer comprising tungsten. A conductive seed layer is produced on the first conductive layer, the contact structure being produced by electroplating on the seed layer. The first conductive layer serves as an etch stop for selectively removing substrate material from the backside.
    Type: Application
    Filed: January 12, 2004
    Publication date: July 14, 2005
    Inventors: Carsten Ahrens, Jakob Huber, Uwe Seidel
  • Patent number: 6873242
    Abstract: The magnetic component uses at least two different layers of magnetic material for carrying and amplifying the magnetic flux. The use of two different layers which may, however, have the same material composition allows the magnetic conductors to form a magnetic circuit with a locally matched domain alignment. The magnetic component accordingly allows considerable improvements to be achieved in the component parameter, in particular a considerable increase in the Q-factor.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: March 29, 2005
    Assignee: Infineon Technologies AG
    Inventors: Carsten Ahrens, Ulf Bartl, Wolfgang Hartung, Reinhard Losehand, Hubert Werthmann
  • Publication number: 20050040430
    Abstract: A diode circuit includes a pin diode structure, wherein the n-semiconductor layer is a buried layer, on which the i-area is deposited by an epitaxy method, and wherein a p-semiconductor layer is introduced into the epitaxy layer. A contacting of the p-semiconductor layer and a contacting of the n-semiconductor layer are arranged on the same main surface of the semiconductor substrate so that an integration with an integrated capacitor, an integrated resistor and/or an integrated inductor is possible.
    Type: Application
    Filed: June 10, 2004
    Publication date: February 24, 2005
    Applicant: Infineon Technologies AG
    Inventors: Carsten Ahrens, Wolfgang Hartung, Holger Heuermann, Reinhard Losehand, Josef-Paul Schaffer
  • Publication number: 20050013090
    Abstract: A capacitor includes a semiconductor substrate in which a trench is formed through which the substrate is doped. A dielectric layer covers the surface of the trench, wherein furthermore an electrically conductive material is arranged in the trench. A first contact structure for contacting the electrically conductive material in the trench in an electrically conductive manner and a second contact structure for contacting the doped semiconductor substrate in an electrically conductive manner are also formed in the capacitor. The capacitor has low series resistance of the electrodes and may be produced in a simple manner.
    Type: Application
    Filed: May 25, 2004
    Publication date: January 20, 2005
    Applicant: Infineon Technologies AG
    Inventors: Carsten Ahrens, Angelika Geiselbrechtinger, Wolfgang Hartung, Christian Herzum, Reinhard Losehand
  • Publication number: 20040191569
    Abstract: The magnetic component uses at least two different layers of magnetic material for carrying and amplifying the magnetic flux. The use of two different layers which may, however, have the same material composition allows the magnetic conductors to form a magnetic circuit with a locally matched domain alignment. The magnetic component accordingly allows considerable improvements to be achieved in the component parameter, in particular a considerable increase in the Q-factor.
    Type: Application
    Filed: March 10, 2004
    Publication date: September 30, 2004
    Inventors: Carsten Ahrens, Ulf Bartl, Wolfgang Hartung, Reinhard Losehand, Hubert Werthmann
  • Patent number: 6798042
    Abstract: The invention is a diode having at least one trench in the semiconductor substrate and insulation configured on the surface of the semiconductor substrate so that the trench limits the depletion region of the diode and the area over which an electrode is in direct contact with the diffusion region of the diode is limited by the insulation. The diode has the advantage that the extent of the depletion region, and thus the area capacitance of the diode, and the size of the electrode are decoupled from one another. The lateral extent of the depletion region can be chosen independently of the size of the electrode.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: September 28, 2004
    Assignee: Infineon Technologies AG
    Inventors: Carsten Ahrens, Raimund Peichl, Reinhard Gabl
  • Publication number: 20030062581
    Abstract: The invention is a diode having at least one trench in the semiconductor substrate and insulation configured on the surface of the semiconductor substrate so that the trench limits the depletion region of the diode and the area over which an electrode is in direct contact with the diffusion region of the diode is limited by the insulation. The diode has the advantage that the extent of the depletion region, and thus the area capacitance of the diode, and the size of the electrode are decoupled from one another. The lateral extent of the depletion region can be chosen independently of the size of the electrode.
    Type: Application
    Filed: October 15, 2002
    Publication date: April 3, 2003
    Inventors: Carsten Ahrens, Raimund Peichl, Reinhard Gabl