Abstract: An electronic device is described which includes at least two sampling circuits, and at least two switching stages configured in parallel. Each of the switching stages is coupled to one of the sampling circuits. The sampling circuits and the switching stages enable the electronic device to exhibit more than two quantization states. The electronic device further includes clock generation circuitry for generating independent clock signals for each of the sampling circuits.

Abstract: An offset voltage calibration circuit for use with a digital switching amplifier. The calibration circuit includes an analog-to-digital converter for converting at least one DC offset voltage associated with the digital switching amplifier to digital offset data. A memory stores the digital offset data. Control circuitry controls the analog-to-digital converter. A digital-to-analog converter coupled to the memory receives the digital offset data and generates an offset compensation voltage for applying to an input port of the digital switching amplifier which thereby cancels at least a portion of the at least one DC offset voltage.

Abstract: Band pass amplifiers and methods for driving the same are described. According to one embodiment, a frequency selective network is provided in a feedback loop. An analog-to-digital converter is coupled to the frequency selective network. A switching stage is coupled to the analog-to-digital converter for producing a continuous-time output signal. The switching stage includes at least one resonance circuit configured to resonate at a resonance frequency and thereby generate at least a portion of the continuous-time output signal. A continuous-time feedback path continuously senses and feeds back the continuous-time output signal to the frequency selective network.

Abstract: Methods and apparatus are described for switching a switch from a first logic state to a second logic state. The switch has a gate terminal having a gate capacitance and a resistance associated therewith. The gate terminal also has a series inductance coupled thereto. While the switch is in the first logic state, a pulse corresponding to the second logic state is applied to the inductance. The pulse has a first level of energy associated therewith which is sufficiently high to overcome damping by the resistance (thus allowing the gate terminal to reach a signal level corresponding to the second logic state thereby switching the switch to the second logic state), and sufficiently low to mitigate oscillation due to the inductance and the gate capacitance (such that the gate terminal settles at the signal level before a subsequent transition of the switch to the first logic state).

Abstract: An electronic device includes sampling circuitry and at least one switching device. Each switching device has resonance circuitry associated with the output terminal thereof. The resonance circuitry and the at least one switching device have at least one resonance oscillation associated therewith. The electronic device further comprises clock generation circuitry which generates a clock signal for the sampling circuitry at least in part from the at least one resonance oscillation.

Abstract: A modulator loop is described having an associated band pass frequency range and including a switching stage having a first delay associated therewith. The modulator loop also includes a modulator stage having a feedback input. The output of the modulator stage is coupled to the input of the switching stage. A first feedback path is coupled between the output of the switching stage and the modulator stage. A notch filter corresponding to the band pass frequency range is coupled between the output of the modulator stage and the feedback input of the modulator stage for compensating for the first delay.

Abstract: A signal processing circuit and method for processing an input signal are described. The circuit includes a frequency selective network, an amplification stage, and at least one continuous-time feedback path from the output of the amplification stage to the frequency selective network. The amplification stage includes a switching amplifier and an analog amplifier. Switching circuitry alternately enables the switching and analog amplifiers for processing of the input signal.

Abstract: An electronic device is described which includes at least two sampling circuits, and at least two switching stages configured in parallel. Each of the switching stages is coupled to one of the sampling circuits. The sampling circuits and the switching stages enable the electronic device to exhibit more than two quantization states. The electronic device further includes clock generation circuitry for generating independent clock signals for each of the sampling circuits.

Abstract: A signal processing circuit is described including a frequency selective network in a feedback loop. An analog-to-analog converter in the feedback loop is coupled to the frequency selective network. A continuous-time feedback path provides feedback from the output terminal of the analog-to-analog converter to the frequency selective network.

Abstract: A signal processing circuit is described including a frequency selective network in a feedback loop. An analog-to-analog converter in the feedback loop is coupled to the frequency selective network. A continuous-time feedback path provides feedback from the output terminal of the analog-to-analog converter to the frequency selective network.

Abstract: A signal processing circuit and method for processing an input signal are described. The circuit includes a frequency selective network, an amplification stage, and at least one continuous-time feedback path from the output of the amplification stage to the frequency selective network. The amplification stage includes a switching amplifier and an analog amplifier. Switching circuitry alternately enables the switching and analog amplifiers for processing of the input signal.

Abstract: A signal processing circuit is described including a frequency selective network in a feedback loop. An analog-to-analog converter in the feedback loop is coupled to the frequency selective network. A continuous-time feedback path provides feedback from the output terminal of the analog-to-analog converter to the frequency selective network.

Abstract: A signal processing circuit and method for processing an input signal are described. The circuit includes a frequency selective network, an amplification stage, and at least one continuous-time feedback path from the output of the amplification stage to the frequency selective network. The amplification stage includes a switching amplifier and an analog amplifier. Switching circuitry alternately enables the switching and analog amplifiers for processing of the input signal.

Abstract: A control circuit for controlling a level of an audio signal and transmitting the signal to an amplifier is described. The control circuit is based on an R-2R resistor network having a plurality of resistor nodes. A plurality of switches alternately connects each of the plurality of resistor nodes to one of a plurality of low impedance nodes and a low impedance input node associated with the amplifier. Switch control circuitry selectively controls the plurality of switches to transmit the audio signal to the low impedance input node.

Abstract: Methods and apparatus for operating first and second switches arranged in a half-bridge configuration are described. First and second gate voltages on the first and second gates, respectively, of the first and second switches are controlled such that the first switch is on and the second switch is off. One of the first and second gate voltages is controlled such that the corresponding one of the first and second switches operates as a constant current source. After one of the first and second switches has been operating as a constant current source, the second gate voltage is controlled such that the second switch is on and the first gate voltage is controlled such that the first switch is off.

Abstract: The transition time of power switching devices ultimately limits the rate at which such devices can be switched. Because the occurrence of unacceptably narrow pulses is relatively rare in an oversampled, noise-shaping signal processor, the elimination of such narrow pulses is introduced through the use of circuitry in the modulator loop which constrains the time between transitions to be greater than or equal to some minimum time period which, in turn provides for a smooth interface to power switching devices. However, because of the delay introduced by this pulse qualification circuitry, the modulator loop sampling frequency is increased to deal with any resulting instability. Thus, an oversampled, noise shaping signal processor is described having at least one integrator stage in a feedback loop. A sampling stage in the feedback loop is coupled to the at least one integrator stage. The sampling stage samples an analog signal at a sample frequency.

Abstract: A modulator loop designed to operate in a frequency range of interest is described. The loop includes a loop output terminal and a switching stage, the output of which is coupled to the loop output terminal. The switching stage has a first delay associated therewith. The output of a modulator stage is coupled to the input of the switching stage. A first feedback path is coupled between the loop output terminal and the feedback input of the modulator stage. A feedback filter is coupled between the output of the modulator stage and the feedback input of the modulator stage which compensates for the first delay. The feedback filter is operable to transmit frequencies outside the frequency range of interest and attenuate frequencies in the frequency range of interest.

Abstract: A signal processing circuit is provided which includes a frequency selective network in a feedback loop for noise shaping purposes. A sampling analog-to-digital converter in the feedback loop operates at a sample frequency substantially above the Nyquist frequency. A switching device is driven by the sampling analog-to-digital converter and produces a continuous-time output signal which is continuously monitored by and fed back to the frequency selective network for noise and distortion correction in the feedback loop. This is in contrast to traditional techniques which employ only state feedback. State feedback (i.e., digital or sampled) of the output of the analog-to-digital converter may also be employed in combination with the continuous-time feedback of the switching device output.

Abstract: A filter transconductance cell utilizes a differential gain stage which operates with a low voltage supply. The filter transconductance cell also includes a negative impedance converter to provide the cell with a high differential output impedance. The filter transconductance cell further includes an arrangement for sensing of a common-mode signal at the input of the differential gain stage and for generating in response thereto a current which is added to each common-mode current at the output of the differential gain stage to thereby produce common-mode rejection.

Abstract: A high output impedance setter utilizes a feedback loop to optimally set the gain of a negative impedance converter within a transconductance cell current source to thereby achieve a virtually infinite differential output impedance. The high output impedance setter also utilizes an operational amplifier to offset the inputs of a transconductance cell for a predetermined period commencing upon the application of power to the setter.