Patents by Inventor Caspar Leendertz

Caspar Leendertz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11075290
    Abstract: A power semiconductor device includes an active region surrounded by an inactive termination region each formed by part of a semiconductor body. The active region conducts load current between first and second load terminals. At least one power cell has trenches extending into the semiconductor body adjacent to each other along a first lateral direction and having a stripe configuration that extends along a second lateral direction into the active region. The trenches spatially confine a plurality of mesas each having at least one first type mesa electrically connected to the first load terminal and configured to conduct at least a part of the load current, and at least one second type mesa configured to not conduct the load current. A decoupling structure separates at least one of the second type mesas into a first section in the active region and a second section in the termination region.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: July 27, 2021
    Assignees: Infineon Technologies AG, Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Matteo Dainese, Alexander Philippou, Markus Bina, Ingo Dirnstorfer, Erich Griebl, Christian Jaeger, Johannes Georg Laven, Caspar Leendertz, Frank Dieter Pfirsch
  • Publication number: 20210226015
    Abstract: A silicon carbide substrate has a trench extending from a main surface of the silicon carbide substrate into the silicon carbide substrate. The trench has a trench width at a trench bottom. A shielding region is formed in the silicon carbide substrate. The shielding region extends along the trench bottom. In at least one doping plane extending approximately parallel to the trench bottom, a dopant concentration in the shielding region over a lateral first width deviates by not more than 10% from a maximum value of the dopant concentration. The first width is less than the trench width and is at least 30% of the trench width.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Inventors: Andreas Peter Meiser, Caspar Leendertz, Anton Mauder
  • Publication number: 20210193435
    Abstract: In an example, a substrate is oriented to a target axis, wherein a residual angular misalignment between the target axis and a preselected crystal channel direction in the substrate is within an angular tolerance interval. Dopant ions are implanted into the substrate using an ion beam that propagates along an ion beam axis. The dopant ions are implanted at implant angles between the ion beam axis and the target axis. The implant angles are within an implant angle range. A channel acceptance width is effective for the preselected crystal channel direction. The implant angle range is greater than 80% of a sum of the channel acceptance width and twofold the angular tolerance interval. The implant angle range is smaller than 500% of the sum of the channel acceptance width and twofold the angular tolerance interval.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 24, 2021
    Inventors: Moriz JELINEK, Michael HELL, Caspar LEENDERTZ, Kristijan Luka MLETSCHNIG, Hans-Joachim SCHULZE
  • Publication number: 20210159172
    Abstract: A semiconductor device is provided. In an embodiment, the semiconductor device comprises a control region, a first power region, a second power region, an isolation region and/or a short circuit structure. The control region comprises a control terminal. The first power region comprises a first power terminal. The second power region comprises a second power terminal. The isolation region is between the control region and the first power region. The short circuit structure extends from the first power region, through the isolation region, to the control region. The short circuit structure is configured to form a low-resistive connection between the control region and the first power region during a failure state of the semiconductor device.
    Type: Application
    Filed: November 27, 2019
    Publication date: May 27, 2021
    Inventors: Thomas BASLER, Andreas HUERNER, Caspar LEENDERTZ, Dethard PETERS
  • Patent number: 11011606
    Abstract: A silicon carbide substrate has a trench extending from a main surface of the silicon carbide substrate into the silicon carbide substrate. The trench has a trench width at a trench bottom. A shielding region is formed in the silicon carbide substrate. The shielding region extends along the trench bottom. In at least one doping plane extending approximately parallel to the trench bottom, a dopant concentration in the shielding region over a lateral first width deviates by not more than 10% from a maximum value of the dopant concentration. The first width is less than the trench width and is at least 30% of the trench width.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 18, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Caspar Leendertz, Anton Mauder
  • Patent number: 11011629
    Abstract: A power semiconductor switch includes a cross-trench structure associated with at least one IGBT cell. The cross-trench structure merge at least one control trench, at least one dummy trench and at least one further trench of at least one IGBT cell to each other. The cross-trench structure overlaps at least partially along a vertical direction with trenches of the at least one IGBT-cell.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: May 18, 2021
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Markus Beninger-Bina, Matteo Dainese, Ingo Dirnstorfer, Erich Griebl, Caspar Leendertz, Christian Philipp Sandow
  • Publication number: 20210134977
    Abstract: A semiconductor device includes a transistor having a drift region of a first conductivity type in a semiconductor substrate having a first main surface, a body region of a second conductivity type between the drift region and first main surface, and trenches in the first main surface which pattern the substrate into mesas. The trenches include an active trench and first and second source trenches. A source region of the first conductivity type is in a first mesa arranged adjacent to the active trench. A second mesa between the first and second source trenches is in contact with at least one source trench. A barrier region of the first conductivity type at a higher doping concentration than the drift region is arranged between the body and drift regions in the second mesa. A vertical size of the barrier region is at least twice a width of the second mesa.
    Type: Application
    Filed: January 8, 2021
    Publication date: May 6, 2021
    Inventors: Caspar Leendertz, Markus Beninger-Bina, Matteo Dainese, Alice Pei-Shan Leendertz, Christian Philipp Sandow
  • Publication number: 20210118986
    Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.
    Type: Application
    Filed: December 4, 2020
    Publication date: April 22, 2021
    Inventors: Thomas Aichinger, Wolfgang Bergner, Paul Ellinghaus, Rudolf Elpelt, Romain Esteve, Florian Grasse, Caspar Leendertz, Shiqin Niu, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
  • Patent number: 10985248
    Abstract: Embodiments of SiC devices and corresponding methods of manufacture are provided. In some embodiments, the SiC device has shielding regions at the bottom of some gate trenches and non-linear junctions formed with the SiC material at the bottom of other gate trenches. In other embodiments, the SiC device has the shielding regions at the bottom of the gate trenches and arranged in rows which run in a direction transverse to a lengthwise extension of the trenches. In still other embodiments, the SiC device has the shielding regions and the non-linear junctions, and wherein the shielding regions are arranged in rows which run in a direction transverse to a lengthwise extension of the trenches.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: April 20, 2021
    Assignee: Infineon Technologies AG
    Inventors: Caspar Leendertz, Romain Esteve, Anton Mauder, Andreas Meiser, Bernd Zippelius
  • Publication number: 20210104605
    Abstract: A SiC substrate of a semiconductor device includes: a drift region of a first conductivity type; a body region of a second conductivity type having a channel region which adjoins a first surface of the SiC substrate; a source region of the first conductivity type adjoining a first end of the channel region; an extension region of the first conductivity type at an opposite side of the body region as the source region and vertically extending to the drift region; a buried region of the second conductivity type below the body region and having a tail which extends toward the first surface and adjoins the extension region; and a compensation region of the first conductivity type protruding from the extension region into the body region along the first surface and terminating at a second end of the channel region opposite the first end.
    Type: Application
    Filed: October 7, 2019
    Publication date: April 8, 2021
    Inventors: Michael Hell, Rudolf Elpelt, Caspar Leendertz, Dethard Peters
  • Publication number: 20210091184
    Abstract: A semiconductor device includes a silicon carbide semiconductor body. A first shielding region of a first conductivity type is connected to a first contact at a first surface of the silicon carbide semiconductor body. A current spread region of a second conductivity type is connected to a second contact at a second surface of the silicon carbide semiconductor body. A doping concentration profile of the current spread region includes peaks along a vertical direction perpendicular to the first surface. A doping concentration of one peak or one peak-group of the peaks is at least 50% higher than a doping concentration of any other peak of the current spread region. A vertical distance between the one peak or the one peak-group of the current spread region and the first surface is larger than a second vertical distance between the first surface and a maximum doping peak of the first shielding region.
    Type: Application
    Filed: September 24, 2020
    Publication date: March 25, 2021
    Inventors: Michael Hell, Rudolf Elpelt, Thomas Ganner, Caspar Leendertz
  • Patent number: 10957768
    Abstract: A SiC substrate of a semiconductor device includes: a drift region of a first conductivity type; a body region of a second conductivity type having a channel region which adjoins a first surface of the SiC substrate; a source region of the first conductivity type adjoining a first end of the channel region; an extension region of the first conductivity type at an opposite side of the body region as the source region and vertically extending to the drift region; a buried region of the second conductivity type below the body region and having a tail which extends toward the first surface and adjoins the extension region; and a compensation region of the first conductivity type protruding from the extension region into the body region along the first surface and terminating at a second end of the channel region opposite the first end.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: March 23, 2021
    Assignee: Infineon Technologies AG
    Inventors: Michael Hell, Rudolf Elpelt, Caspar Leendertz, Dethard Peters
  • Publication number: 20210050421
    Abstract: A silicon carbide device includes a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body. The gate structure has a gate length along a lateral first direction. A bottom surface and an active first gate sidewall of the gate structure are connected via a first bottom edge of the gate structure. The silicon carbide device further includes at least one source region of a first conductivity type. A shielding region of a second conductivity type is in contact with the first bottom edge of the gate structure across at least 20% of the gate length.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 18, 2021
    Inventors: Caspar Leendertz, Thomas Basler, Paul Ellinghaus, Rudolf Elpelt, Michael Hell, Jens Peter Konrath, Shiqin Niu, Dethard Peters, Konrad Schraml, Bernd Leonhard Zippelius
  • Patent number: 10923578
    Abstract: A semiconductor device includes a transistor. The transistor includes a drift region of a first conductivity type in a semiconductor substrate having a first main surface, a body region of a second conductivity type between the drift region and the first main surface, and a plurality of trenches in the first main surface and patterning the semiconductor substrate into a plurality of mesas including a first mesa and a dummy mesa. The plurality of trenches includes at least one active trench. The first mesa is arranged at a first side of the active trench, and the dummy mesa is arranged at a second side of the active trench. A gate electrode is arranged in the active trench, and a source region of the first conductivity type is in the first mesa. A one-sided channel of the transistor is configured to be formed in the first mesa.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: February 16, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Caspar Leendertz, Markus Bina, Matteo Dainese, Alice Pei-Shan Hsieh, Christian Philipp Sandow
  • Publication number: 20210043759
    Abstract: A power semiconductor device includes an active cell region with a drift region of a first conductivity type, a plurality of IGBT cells arranged within the active cell region, each of the IGBT cells includes at least one trench that extends into the drift, an edge termination region surrounding the active cell region, a transition region arranged between the active cell region and the edge termination region, at least some of the IGBT cells are arranged within or extend into the transition region, a barrier region of a second conductivity type, the barrier region is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells and does not extend into the transition region, and a first load terminal and a second load terminal, the power semiconductor device is configured to conduct a load current along a vertical direction between.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Inventors: Alexander Philippou, Markus Beninger-Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Francisco Javier Santos Rodriguez, Antonio Vellei, Caspar Leendertz, Christian Philipp Sandow
  • Patent number: 10903322
    Abstract: Embodiments of SiC devices and corresponding methods of manufacture are provided. In some embodiments, the SiC device has shielding regions at the bottom of some gate trenches and non-linear junctions formed with the SiC material at the bottom of other gate trenches. In other embodiments, the SiC device has the shielding regions at the bottom of the gate trenches and arranged in rows which run in a direction transverse to a lengthwise extension of the trenches. In still other embodiments, the SiC device has the shielding regions and the non-linear junctions, and wherein the shielding regions are arranged in rows which run in a direction transverse to a lengthwise extension of the trenches.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: January 26, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Caspar Leendertz, Anton Mauder
  • Patent number: 10896952
    Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: January 19, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Wolfgang Bergner, Paul Ellinghaus, Rudolf Elpelt, Romain Esteve, Florian Grasse, Caspar Leendertz, Shiqin Niu, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
  • Publication number: 20210013310
    Abstract: First dopants are implanted through a larger opening of a first process mask into a silicon carbide body, wherein the larger opening exposes a first surface section of the silicon carbide body. A trench is formed in the silicon carbide body in a second surface section exposed by a smaller opening in a second process mask. The second surface section is a sub-section of the first surface section. The larger opening and the smaller opening are formed self-aligned to each other. At least part of the implanted first dopants form at least one compensation layer portion extending parallel to a trench sidewall.
    Type: Application
    Filed: July 11, 2020
    Publication date: January 14, 2021
    Inventors: Caspar Leendertz, Romain Esteve, Moriz Jelinek, Anton Mauder, Hans-Joachim Schulze, Werner Schustereder
  • Publication number: 20200381253
    Abstract: A silicon carbide substrate is provided that includes a drift layer of a first conductivity type and a trench extending from a main surface of the silicon carbide substrate into the drift layer. First dopants are implanted through a first trench sidewall of the trench. The first dopants have a second conductivity type and are implanted at a first implant angle into the silicon carbide substrate, wherein at the first implant angle channeling occurs in the silicon carbide substrate. The first dopants form a first compensation layer extending parallel to the first trench sidewall.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 3, 2020
    Inventors: Hans-Joachim SCHULZE, Romain ESTEVE, Moriz JELINEK, Caspar LEENDERTZ, Werner SCHUSTEREDER
  • Patent number: 10840362
    Abstract: A power semiconductor device includes an active cell region with a drift region, and IGBT cells at least partially arranged within the active cell region. Each IGBT cell includes at least one trench extending into the drift region along a vertical direction, an edge termination region surrounding the active cell region, and a transition region arranged between the active cell region and the edge termination region. The transition region has a width along a lateral direction from the active cell region towards the edge termination region. At least some of the IGBT cells are arranged within, or, respectively, extend into the transition region. An electrically floating barrier region of each IGBT cell is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells. The electrically floating barrier region does not extend into the transition region.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: November 17, 2020
    Assignee: Infineon Technologies AG
    Inventors: Alexander Philippou, Markus Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Francisco Javier Santos Rodriguez, Antonio Vellei, Caspar Leendertz, Christian Philipp Sandow