Abstract: The invention includes a method of cleaning a processing chamber by introducing supercritical fluid into the processing chamber. A residue over an internal chamber surface is contacted with the supercritical fluid to remove the residue from the surface. The invention also includes a method of removing deposited material from internal surfaces of a processing system. A cleaning agent comprising at least one of C3H8, C2H6 and CH4 is provided in supercritical phase into at least a portion of the processing system. A material deposited on an internal surface of the processing system is contacted with the cleaning agent to remove at least a portion of the deposited material.

Abstract: An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al2O3), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al2O3) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.

Abstract: A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes are supported at least in part with a retaining structure which engages the sidewalls, with the retaining structure comprising a fluid previous material. A capacitor dielectric material is deposited over the capacitor electrodes through the fluid previous material of the retaining structure effective to deposit capacitor dielectric material over portions of the sidewalls received below the retaining structure. Capacitor electrode material is deposited over the capacitor dielectric material through the fluid previous material of the retaining structure effective to deposit capacitor electrode material over at least some of the capacitor dielectric material received below the retaining structure. Integrated circuitry independent of method of fabrication is also contemplated.

Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.

Abstract: A method and apparatus are presented for reducing halide-based contamination within deposited titanium-based thin films. Halide adsorbing materials are utilized within the deposition chamber to remove halides, such as chlorine and chlorides, during the deposition process so that contamination of the titanium-based film is minimized. A method for regenerating the halide adsorbing material is also provided.

Abstract: The invention includes a capacitor construction. A capacitor electrode has a perovskite-type dielectric material thereover. The perovskite-type dielectric material has an edge region proximate the electrode, and a portion further from the electrode than the edge region. The portion has a different amount of crystallinity than the edge region. The invention also includes a method of forming a capacitor construction. A capacitor electrode is provided, and a perovskite-type dielectric material is chemical vapor deposited over the first capacitor electrode. The depositing includes flowing at least one metal organic precursor into a reaction chamber and forming a component of the perovskite-type dielectric material from the precursor. The precursor is exposed to different oxidizing conditions during formation of the perovskite-type dielectric material so that a first region of the dielectric material has more amorphous character than a second region of the dielectric material.

Abstract: A semiconductor device of unipolar type has Schottky-contacts (6) laterally separated by regions in the form of additional layers (7, 7?) of semiconductor material on top of a drift layer (3). Said additional layers being doped according to a conductivity type being opposite to the one of the drift layer. At least one (7?) of the additional layers has a substantially larger lateral extension and thereby larger area of the interface to the drift layer than adjacent such layers (7) for facilitating the building-up of a sufficient voltage between that layer and the drift layer for injecting minority charge carriers into the drift layer upon surge for surge protection.

Abstract: The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.

Abstract: One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.

Abstract: One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.

Abstract: A vertical junction field effect transistor includes a trench formed in an epitaxial layer. The trench surrounds a channel region of the epitaxial layer. The channel region may have a graded or uniform dopant concentration profile. An epitaxial gate structure is formed within the trench by epitaxial regrowth. The epitaxial gate structure may include separate first and second epitaxial gate layers, and may have either a graded or uniform dopant concentration profile.

Abstract: The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.

Abstract: Embodiments related to a method of forming semi-insulating silicon carbide (SiC) single crystal are disclosed in which shallow donor levels originating, at least in part, from residual nitrogen impurities are compensated by the addition of one or more trivalent element(s) introduced by doping the SiC in a concentration that changes the SiC conductivity from n-type to semi-insulating. Related embodiments provide for the additional doping of the SiC single crystal with one or more deep level dopants. However, the resulting concentration of deep level dopants, as well as shallow donor or acceptor dopants, is not limited to concentrations below the detection limits of secondary ion mass spectrometry (SIMS) analysis.

Abstract: The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material is masked. A first silicon-comprising layer is epitaxially grown from the exposed monocrystalline material of the first portion and not from the monocrystalline material of the masked second portion. After growing the first silicon-comprising layer, the second portion of the monocrystalline material is unmasked. A second silicon-comprising layer is then epitaxially grown from the first silicon-comprising layer and from the unmasked monocrystalline material of the second portion. Other aspects and implementations are contemplated.

Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.

Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.

Abstract: An interface forming method includes forming a first layer containing a first chemical element and chemisorbing on the first layer an interface layer containing at least one monolayer of the first chemical element intermixed with a second chemical element different from the first chemical element. A second layer comprising the second chemical element can be formed on the interface layer. The first layer might not substantially contain the second chemical element, the second layer might not substantially contain the first chemical element, or both. An apparatus can include a first layer containing a first chemical element, an interface layer chemisorbed on the first layer, and a second layer containing a second element on the interface layer. The interface layer can contain at least one monolayer of the first chemical element intermixed with a second chemical element different from the first chemical element.

Abstract: A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g. ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boundaries of the metal layer, e.g., platinum, to oxidize a metal layer thereon, e.g, ruthenium layer. The structure is particularly advantageous for use in capacitor structures and memory devices, such as dynamic random access memory (DRAM) devices.

Abstract: An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. The first precursor gas flowing comprises a plurality of first precursor gas pulses. The plurality of first precursor gas pulses comprises at least one total period of time between two immediately adjacent first precursor gas pulses when no gas is fed to the chamber. After forming the first monolayer on the substrate, a second precursor gas different in composition from the first is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.

Abstract: One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.